The 22 nanometer (22 nm) node is the process step following the 32 nm in CMOS semiconductor device fabrication. The typical half-pitch (i.e., half the distance between identical features in an array) for a memory cell using the process is around 22 nm. It was first introduced by semiconductor companies in 2008 for use in memory products, while first consumer-level CPU deliveries started in April 2012.
The ITRS 2006 Front End Process Update indicates that equivalent physical oxide thickness will not scale below 0.5 nm (about twice the diameter of a silicon atom), which is the expected value at the 22 nm node. This is an indication that CMOS scaling in this area has reached a wall at this point, possibly disturbing Moore's law.
20 nanometer is an intermediate half-node die shrink based on the 22 nanometer process.
The 22 nm process was superseded by commercial 14 nm technology in 2014.
On August 18, 2008, AMD, Freescale, IBM, STMicroelectronics, Toshiba, and the College of Nanoscale Science and Engineering (CNSE) announced that they jointly developed and manufactured a 22 nm SRAM cell, built on a traditional six-transistor design on a 300 mm wafer, which had a memory cell size of just 0.1 μm2. The cell was printed using immersion lithography.
The 22 nm node may be the first time where the gate length is not necessarily smaller than the technology node designation. For example, a 25 nm gate length would be typical for the 22 nm node.
On September 22, 2009, during the Intel Developer Forum Fall 2009, Intel showed a 22 nm wafer and announced that chips with 22 nm technology would be available in the second half of 2011. SRAM cell size is said to be 0.092 μm2, smallest reported to date.
On April 23, 2012, Intel Core i7 and Intel Core i5 processors based on Intel's Ivy Bridge 22 nm technology for series 7 chipsets went on sale worldwide. Volume production of 22 nm processors began more than six months earlier, as confirmed by former Intel CEO Paul Otellini on October 19, 2011.
- TG Daily news report
- EETimes news report
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|CMOS manufacturing processes||Succeeded by