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An AI accelerator is (as of 2016) an emerging class of microprocessor or computer system designed to accelerate artificial neural networks, machine vision and other machine learning algorithms for robotics, internet of things and other data-intensive or sensor-driven tasks. They are sometimes manycore designs (mirroring the massively-parallel nature of biological neural networks). Many vendor-specific terms exist for devices in this space.
- 1 History of AI acceleration
- 2 Emergence of dedicated AI accelerator ASICs
- 3 Nomenclature
- 4 Potential applications
- 5 Examples
- 6 See also
- 7 References
- 8 External links
History of AI acceleration
Computer systems have frequently complemented the CPU with special purpose accelerators for intensive tasks, most notably graphics, but also sound, video, etc. Over time various accelerators have appeared that have been applicable to AI workloads.
In the early days, DSPs (such as the AT&T DSP32C) have been used as neural network accelerators e.g. to accelerate OCR software, and there have been attempts to create parallel high throughput systems for workstations (e.g. TetraSpert in the 1990s, which was a parallel fixed-point vector processor), aimed at various applications including neural network simulations. FPGA-based accelerators were also first explored in the 1990s for both inference and training. ANNA was a neural net CMOS accelerator developed by Yann LeCun. There was another attempt to build a neural net workstation called Synapse-1 (not to be confused with the current IBM SyNAPSE project).
Architectures such as the Cell microprocessor have exhibited features significantly overlaping with AI accelerators - in its support for packed low precision arithmetic, dataflow architecture, and prioritising 'throughput' over latency and "branchy-int" code. This was a move toward heterogeneous computing, with a number of throughput-oriented accelerators intended to assist the CPU with a range of intensive tasks: physics-simulation, AI, video encoding/decoding, and certain graphics tasks beyond its contemporary GPUs.[not in citation given]
The physics processing unit was yet another example of an attempt to fill the gap between CPU and GPU in PC hardware, however physics tends to require 32-bit precision and up, whilst much lower precision can be a better tradeoff for AI.
CPUs themselves have gained increasingly wide SIMD units (driven by video and gaming workloads) and increased the number of cores in a bid to eliminate the need for another accelerator, as well as for accelerating application code. These tend to support packed low precision data types.
Use of GPGPU
Spontaneous innovative software appeared using vertex and pixel shaders for general purpose computation through rendering APIs, by storing non-graphical data in vertex buffers and texture maps (including implementations of convolutional neural networks for OCR), Vendors of graphics processing units subsequently saw the opportunity to expand their market and generalised their shader pipelines with specific support for GPGPU, mostly motivated by the demands of video game-physics but also targeting scientific computing.
This killed off the market for a dedicated physics accelerator, and superseded Cell in video game consoles, and eventually led to their use in running convolutional neural networks such as AlexNet (which exhibited leading performance the ImageNet Large Scale Visual Recognition Challenge).
As such, as of 2016 GPUs are popular for AI work, and they continue to evolve in a direction to facilitate deep learning, both for training and inference in devices such as self-driving cars. - and gaining additional connective capability for the kind of dataflow workloads AI benefits from (e.g. Nvidia NVLink).
Use of FPGA
Deep learning frameworks are still evolving, making it hard to design custom hardware. Reconfigurable devices like field-programmable gate arrays (FPGA) make it easier to evolve hardware, frameworks and software alongside each other.
Microsoft has used FPGA chips to accelerate inference. This has motivated Intel to purchase Altera with the aim of integrating FPGAs in server CPUs, which would be capable of accelerating AI as well as other tasks.
Emergence of dedicated AI accelerator ASICs
Whilst GPUs and FPGAs perform far better than CPUs for these tasks, a factor of 10 in efficiency can still be gained with a more specific design, via an application-specific integrated circuit (ASIC).
Memory access pattern
The memory access pattern of AI calculations differs from graphics: a more predictable but deeper dataflow, benefiting more from the ability to keep more temporary variables on-chip (e.g. in scratchpad memory rather than caches); GPUs by contrast devote silicon to efficiently dealing with highly non-linear gather-scatter addressing between texture maps and frame-buffers, and texture filtering, as is needed for their primary role in 3D rendering.
AI researchers are often finding minimal accuracy losses whilst dropping to 16 or even 8 bits, suggesting that a larger volume of low precision arithmetic is a better use of the same bandwidth. Some researchers have even tried using 1-bit precision (i.e. putting the emphasis entirely on spatial information in vision tasks). IBM's design is more radical, dispensing with scalar values altogether and accumulating timed pulses to represent activations stochastically, requiring conversion of traditional representations.
Slowing of Moore's law
As of 2016, the slowing (and possible end of) Moore's law drives some to suggest refocusing industry efforts on application led silicon design, whereas in the past, increasingly powerful general purpose chips have been applied to varying applications via software. In this scenario, a diversification of dedicated AI accelerators makes more sense than continuing to stretch GPUs and CPUs.
As of 2016, the field is still in flux and vendors are pushing their own marketing term for what amounts to an "AI accelerator", in the hope that their designs and APIs will dominate. There is no consensus on the boundary between these devices, nor the exact form they will take, however several examples clearly aim to fill this new space, with a fair amount of overlap in capabilities.
In the past when consumer graphics accelerators emerged, the industry eventually adopted Nvidia's self-assigned term, "the GPU", as the collective noun for "graphics accelerators", which had taken many forms before settling on an overall pipeline implementing a model presented by Direct3D.
- Autonomous cars, Nvidia have targeted their Drive PX-series boards at this space.
- Military robots
- Agricultural robots, for example chemical-free weed control.
- Voice control, e.g. in mobile phones, a target for Qualcomm Zeroth.
- Machine translation
- Unmanned aerial vehicles, e.g. navigation systems, e.g. the Movidius Myriad 2 has been demonstrated successfully guiding autonomous drones.
- Industrial robots, increasing the range of tasks that can be automated, by adding adaptability to variable situations.
- Healthcare assisting with diagnoses
- Search engines, increasing the energy efficiency of data centres and ability to use increasingly advanced queries.
- Natural language processing
- STMicroelectronics at the start of 2017 presented a demonstrator SoC manufactured in a 28 nm process containing a deep CNN accelerator.
- Cadence Tensilica Vision C5,introduced May 2017, is a neural networks optimized DSP IP core for SoCs. C5 contains 1024 MAC units.
- PowerVR 2NX NNA (Neural Net Accelerator), launched September 2017, is an IP core from Imagination Technologies licensed for integration into chips. It supports four to sixteen bits of precision
- NM500 is the latest as of 2016 in a series of accelerator chips for Radial Basis Function neural nets from General Vision. 
- Huawei's smartphone chip Kirin 970 contains a dedicated ”Neural Processing Unit” (NPU)
- There is a Neural Engine in the Apple iPhone X's A11 Bionic SoC.
- Vision processing units
- Google Tensor processing unit was presented as an accelerator for Google's TensorFlow framework, which is extensively used for convolutional neural networks. It focuses on a high volume of 8-bit precision arithmetic.
- SpiNNaker is a many-core design combining traditional ARM architecture cores with an enhanced network fabric design specialised for simulating a large neural network.
- Accelerators for spiking neural networks:-
- Intel Loihi, introduced in September 2017, is an experimental neuromorphic chip containing 130,000 artificial neurons communicating asynchronously using spiking through 130 million artificial synapses. 
- TrueNorth is a manycore design based on spiking neurons rather than traditional arithmetic. The frequency of pulses represents signal intensity. but some results are promising, with large energy savings demonstrated for vision tasks.
- BrainChip in September 2017 introduced a commercial PCI Express card with a Xilinx Kintex Ultrascale FPGA running neuromorphic neural cores applying pattern recognition on 600 video images per second using 16 watts of power.
- IIT Madras is designing a spiking neuron accelerator for new RISC-V systems, aimed at big-data analytics in servers.
- Intel Nervana NNP (Neural Network Processor) (a.k.a. ”Lake Crest”) was available in samples in October 2017. According to Intel this was the first commercially available chip with a purpose built architecture for deep learning. Facebook was a partner in the design process. 
- Eyeriss, a design aimed explicitly at convolutional neural networks, using a scratchpad and on chip network architecture.
- Adapteva epiphany is targeted as a coprocessor, featuring a network on a chip scratchpad memory model, suitable for a dataflow programming model, which should be suitable for many machine learning tasks.
- Kalray have demonstrated an MPPA and report efficiency gains over GPUs for convolutional neural nets.
- Nvidia DGX-1 is based on GPU technology however the use of multiple chips forming a fabric via NVLink specialises its memory architecture in a way that is particularly suitable for deep learning.
- Vathys is building an accelerator that, in contrast to others, uses floating point, not fixed point, a decision which recent papers such as [clarification needed] support.
- Nvidia Volta, augments the GPU with additional 'tensor units' targeted specifically at accelerating calculations for neural networks
- Graphcore IPU, a graph-based AI accelerator
- DPU, by wave computing, a dataflow architecture 
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- "The end of general purpose computers (not)".This presentation covers a past attempt at neural net accelerators, notes the similarity to the modern SLI GPGPU processor setup, and argues that general purpose vector accelerators are the way forward (in relation to RISC-V hwacha project. Argues that NN's are just dense and sparse matrices, one of several recurring algorithms)
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- "yann lecun on IBM truenorth".argues that spiking neurons have never produced leading quality results, and that 8-16 bit precision is optimal, pushes the competing 'neuflow' design
- "IBM cracks open new era of neuromorphic computing".
TrueNorth is incredibly efficient: The chip consumes just 72 milliwatts at max load, which equates to around 400 billion synaptic operations per second per watt — or about 176,000 times more efficient than a modern CPU running the same brain-like workload, or 769 times more efficient than other state-of-the-art neuromorphic approaches
- "BrainChip Accelerator".
- "India preps RISC-V Processors - Shakti targets servers, IoT, analytics".
The Shakti project now includes plans for at least six microprocessor designs as well as associated fabrics and an accelerator chip
- Kampman, Jeff (17 October 2017). "Intel unveils purpose-built Neural Network Processor for deep learning". Tech Report. Retrieved 18 October 2017.
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- Chen, Yu-Hsin; Krishna, Tushar; Emer, Joel; Sze, Vivienne (2016). "Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks". IEEE International Solid-State Circuits Conference, ISSCC 2016, Digest of Technical Papers. pp. 262–263.
- "kalray MPPA" (PDF).
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- "Graphcore Technology".
- "Wave Computing's DPU architecture".