AMD Turion

AMD Turion is the brand name AMD applies to its x86-64 low-power consumption (mobile) processors codenamed K8L.^[1] The Turion 64 and Turion 64 X2/Ultra processors compete with Intel's mobile processors, initially the Pentium M and the Intel Core and Intel Core 2 processors.

Features[edit]

Turion 64[edit]

Earliest Turion 64 processors are plugged into AMD's Socket 754. They are equipped with 512 or 1024 KiB of L2 cache, a 64-bit single channel on-die DDR-400 memory controller, and an 800 MHz HyperTransport bus. Battery saving features, like PowerNow!, are central to the marketing and usefulness of these CPUs. The newer "Richmond" models are designed for AMD's Socket S1 and have a double-channel DDR2 controller.

Turion 64 X2[edit]

Turion 64 X2 is AMD's 64-bit dual-core mobile CPU, intended to compete with Intel's Core and Core 2 CPUs. The Turion 64 X2 was launched on May 17, 2006,^[2] after several delays. These processors use Socket S1 and feature DDR2 memory. They also include AMD Virtualization Technology and more power-saving features.

The earlier 90 nm devices were codenamed Taylor and Trinidad, while the newer 65 nm cores have codename Tyler.

Turion X2 Ultra[edit]

Turion X2 Ultra (codenamed Griffin) is the first processor family from AMD solely for the mobile platform, based on the Athlon 64 (K8 Revision G) architecture with some specific architectural enhancements similar to current Phenom processors aimed at lower power consumption and longer battery life. The Turion Ultra processor was released as part of the "Puma" mobile platform in June 2008.

The Turion X2 Ultra is a dual-core processor fabricated on 65 nm technology using 300 mm SOI wafers. It supports DDR2-800 SO-DIMMs and features a DRAM prefetcher to improve performance and a mobile-enhanced northbridge (memory controller, HyperTransport controller, and crossbar switch). Each processor core comes with 1 MiB L2 cache for a total of 2 MiB L2 cache for the entire processor. This is double the L2 cache found on the Turion 64 X2 processor. Clock rates range from 2.0 GHz to 2.4 GHz, and thermal design power (TDP) range from 32 watts to 35 watts.^[3]

The Turion X2 Ultra processor, unlike earlier Turions, implements three voltage planes: one for the northbridge and one for each core.^[4] This, along with multiple phase-locked loops (PLL), allows one core to alter its voltage and operating frequency independently of the other core, and independently of the northbridge. Indeed, in a matter of microseconds, the processor can switch to one of 8 frequency levels and one of 5 voltage levels. By adjusting frequency and voltage during use, the processor can adapt to different workloads and help reduce power consumption. It can operate as low as 250 MHz to conserve power during light use.

Additionally, the processor features deep sleep state C3, deeper sleep state C4 (AltVID), and HyperTransport 3.0 up to 2.6 GHz, or up to 41.6 GB/s bandwidth per link at 16-bit link width and dynamic scaling of HT link width down to 0-bit ("disconnected") in both directions from and to the chipset for four different usage scenarios.^[5] It also implements multiple on-die thermal sensors through integrated SMBUS (SB-TSI) interface (replaces and eliminates the thermal monitor circuit chip through SMBUS in its predecessors) with additional MEMHOT signal sent from embedded controller to the processor, and reduces memory temperature.

The Turion X2 Ultra processor uses the same socket S1 as its predecessor, Turion 64 X2, but the pinout is different.^[6] It is designed to work with the RS780M chipset.

Given the above enhancements on the architecture, the cores were minimally modified and are based on the K8 instead of the K10 microarchitecture.^[6] AMD Fellow Maurice Steinman has said the cores are almost transistor-for-transistor identical to those found in the 65 nm Turion 64 X2 processors. ^{[citation needed]}

Turion II Ultra[edit]

Turion II Ultra (codenamed Caspian) is the mobile version of the K10.5 architecture produced using 45 nm fabrication process, also known by its desktop variant Regor. It is a dual core processor, and features clock speeds of 2.5 GHz, 2 MB total L2 cache (1 MB per core), HyperTransport at 3.6 GT/s, and a 128 bit FPU. It maintains a TDP of 35W from its predecessor Turion X2 Ultra (codenamed Griffin).

Turion II[edit]

Turion II is identical to Turion II Ultra, except that the Turion II features only 1 MB of L2 cache (512 KB per core), and lower clock speeds ranging from 2.2 GHz to 2.6 GHz.

Model naming methodology[edit]

The model naming scheme does not make it obvious how to compare one Turion with another, or even an Athlon 64. The model name is two letters, a dash, and a two digit number (for example, ML-34). The two letters together designate a processor class, while the number represents a performance rating (PR). The first letter is M for mono (single) core processors and T for twin (dual) core Turion 64 X2 processors. The later in the alphabet that the second letter appears, the more the model has been designed for mobility (frugal power consumption). Take for instance, an MT-30 and an ML-34. Since the T in the MT-30 is later in the alphabet than the L in ML-34, the MT-30 consumes less power than the ML-34. But since 34 is greater than 30, the ML-34 is faster than the MT-30.

The release of the Turion II Ultra and Turion II lineups have simplified name methodology; all newly released Turions have the letter "M" followed by a number designating relative performance. The higher the number, the higher the clock speed. For example, the Turion II M500 has a clock speed of 2.2 GHz while the Turion II M520 has a clock speed of 2.3 GHz.

Cores[edit]

AMD Turion processor family
Code-named	Core	Date released
Lancaster Richmond Sable	solo (90 nm) solo (90 nm) solo (65 nm)	Mar 2005 Sep 2006 Jun 2008
Taylor Trinidad Tyler Lion	dual (90 nm) dual (90 nm) dual (65 nm) dual (65 nm)	May 2006 May 2006 May 2007 Jun 2008
Griffin	dual (65 nm)	Jun 2008
Caspian	dual (45 nm)	Sep 2009
Champlain	dual (45 nm)	May 2010

Lancaster (90 nm SOI)[edit]

Stepping E5
L1 cache: 64 + 64 KiB (data + instructions)
L2 cache: 512 or 1024 KiB, full speed
MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, AMD64, PowerNow!, NX Bit
Socket 754, HyperTransport (800 MHz, HT800)
VCore:
- 0.8 V - 1.2 V for ML chips
- 0.8 V - 1.35 V for MT chips
Power consumption (TDP): 25/35 watt max
First release: August 25, 2005
Clock rate: 1600, 1800, 2000, 2200, 2400 MHz
- 25W TDP:
  - MT-28: 1600 MHz (512 KiB L2-Cache)
  - MT-30: 1600 MHz (1024 KiB L2-Cache)
  - MT-32: 1800 MHz (512 KiB L2-Cache)
  - MT-34: 1800 MHz (1024 KiB L2-Cache)
  - MT-37: 2000 MHz (1024 KiB L2-Cache)
  - MT-40: 2200 MHz (1024 KiB L2-Cache)
- 35W TDP:
  - ML-28: 1600 MHz (512 KiB L2-Cache)
  - ML-30: 1600 MHz (1024 KiB L2-Cache)
  - ML-32: 1800 MHz (512 KiB L2-Cache)
  - ML-34: 1800 MHz (1024 KiB L2-Cache)
  - ML-37: 2000 MHz (1024 KiB L2-Cache)
  - ML-40: 2200 MHz (1024 KiB L2-Cache)
  - ML-42: 2400 MHz (512 KiB L2-Cache)
  - ML-44: 2400 MHz (1024 KiB L2-Cache)

Richmond (90 nm SOI)[edit]

The models support the same features available in Lancaster, plus AMD-V.

L1 cache: 64 + 64 KiB (data + instructions)
L2 cache: 512 KiB, full speed
MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, AMD64, PowerNow!, NX Bit, AMD-V
Socket S1, HyperTransport (800 MHz, HT800)
Power consumption (TDP): 31 watt max
First release: September 1, 2006
Clock rate: 2000, 2200 MHz
- 31W TDP:
  - MK-36: 2000 MHz (512 KiB L2-Cache)
  - MK-38: 2200 MHz (512 KiB L2-Cache)

Taylor & Trinidad (90 nm SOI)[edit]

Dual AMD64 core
Stepping F2
L1 cache: 64 + 64 KiB (data + instructions) per core
L2 cache: 256 KiB (Taylor) or 512 KiB (Trinidad) per core, full speed
Memory controller: dual channel DDR2-667 MHz
MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, PowerNow!, NX bit, AMD-V
Socket S1, HyperTransport (800 MHz, 1600 MT/s, 10.7 GB/s CPU-RAM + 6.4 GB/s CPU-I/O transfer rate)[1]
Power consumption (TDP): 31, 33, 35 watt max
First release: May 17, 2006
Clock rate: 1600, 1800, 2000, 2200 MHz
- 31W TDP:
  - TL-50: 1600 MHz (256 KiB L2-Cache per core)
  - TL-52: 1600 MHz (512 KiB L2-Cache per core)
- 33W TDP:
  - TL-56: 1800 MHz (512 KiB L2-Cache per core)
- 35W TDP:
  - TL-60: 2000 MHz (512 KiB L2-Cache per core)
  - TL-64: 2200 MHz (512 KiB L2-Cache per core)

Tyler (65 nm SOI)[edit]

Dual AMD64 core
Steppings G1, G2
L1 cache: 64 + 64 KiB (data + instructions) per core
L2 cache: 256 KiB per core (All Athlon & Turion TL-50) or 512 KiB per core (All Others), full speed
Memory controller: dual channel DDR2-667 MHz (10.6 GB/s full-duplex CPU/RAM bandwidth)
100 MHz granularity (Dynamic P-state Transitions)
MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, PowerNow!, NX Bit, AMD-V
Socket S1, HyperTransport (800 MHz / 1600 MT/s)
Power consumption (TDP): 31, 35 watt max.
First release: 2007
Clock rate: 1700, 1800, 1900, 2000, 2100, 2200, 2300, 2400 MHz
- 31W TDP:
  - TK-53 1700 MHz (256 KiB L2-Cache per core) - ※Athlon 64 X2 Dual-Core for Notebooks
  - TK-55 1800 MHz (256 KiB L2-Cache per core) - ※Athlon 64 X2 Dual-Core for Notebooks
  - TL-56 1800 MHz (512 KiB L2-Cache per core)
  - TK-57 1900 MHz (256 KiB L2-Cache per core) - ※Athlon 64 X2 Dual-Core for Notebooks
  - TL-58 1900 MHz (512 KiB L2-Cache per core)
  - TL-60 2000 MHz (512 KiB L2-Cache per core)
- 35W TDP:
  - TL-62 2100 MHz (512 KiB L2-Cache per core)
  - TL-64 2200 MHz (512 KiB L2-Cache per core)
  - TL-66 2300 MHz (512 KiB L2-Cache per core)
  - TL-68 2400 MHz (512 KiB L2-Cache per core)

Lion (65 nm SOI)[edit]

Dual AMD64 core
B1 Stepping
L1 cache: 64 + 64 KiB (data + instructions) per core
- L2 cache: 512 KiB per core, full speed, or
- L2 cache: 1 MiB per core, full speed
Memory controller: dual channel DDR2-800 MHz
MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, PowerNow!, NX bit, AMD-V
Socket S1 (S1g2)
HyperTransport (1800 MHz, 3600 MT/s, 12.8 GB/s CPU-RAM + 14.4 GB/s CPU-I/O transfer rate)
HyperTransport (2200 MHz, 4400 MT/s on ZM-85 y ZM-87 only)
Power consumption (TDP): 32, 35 watt max
First release: June 4, 2008
- Clock rate: 2000, 2100, 2200 MHz (RM-7x, L2 cache: 1 MiB)
- Clock rate: 2100, 2200, 2300, 2400, 2500 MHz (ZM-8x, L2 cache: 2 MiB)
- 31W TDP:
  - RM-70: 2000 MHz
- 32W TDP:
  - ZM-80: 2100 MHz
- 35W TDP:
  - RM-72: 2100 MHz
  - RM-74: 2200 MHz
  - ZM-82: 2200 MHz
  - ZM-84: 2300 MHz
  - ZM-85: 2300 MHz
  - ZM-86: 2400 MHz
  - ZM-87: 2400 MHz
  - ZM-88: 2500 MHz

Caspian (45 nm SOI)[edit]

Dual Stars core
- L2 cache: 512 KiB per core, full speed (For Turion II, Athlon II and Sempron II), or
- L2 cache: 1 MiB per core, full speed (For Turion II Ultra)
Memory controller: dual channel DDR2-800 MHz
MMX, Extended 3DNow!, SSE, SSE2, SSE3, SSE4a, AMD64, PowerNow!, NX bit, AMD-V
Socket S1g3
HyperTransport (1800 MHz, 3600 MT/s on M6xx/M5xx models, 1600 MHz, 3200 MT/s for M3xx models)
Power consumption (TDP): 35 watt max
- Clock rate: 2000 (M1xx, L2 cache 512 KiB)
- Clock rate: 2000, 2100, 2200 MHz (M3xx, L2 cache: 1 MiB)
- Clock rate: 2200, 2300, 2400 MHz (M5xx, L2 cache: 1 MiB)
- Clock rate: 2400, 2500, 2600, 2700 MHz (M6xx, L2 cache: 2 MiB)
- 25W TDP:
  - M100: 2000 MHz - Sempron II Single-Core (only 64 bit FPU)
  - M120: 2100 MHz - Sempron II Single-Core (only 64 bit FPU)
- 35W TDP:
  - M300: 2000 MHz – Athlon II Dual-Core (only 64 bit FPU)
  - M320: 2100 MHz – Athlon II Dual-Core (only 64 bit FPU)
  - M340: 2200 MHz – Athlon II Dual-Core (only 64 bit FPU)
  - M500: 2200 MHz – Turion II Dual-Core
  - M520: 2300 MHz – Turion II Dual-Core
  - M540: 2400 MHz – Turion II Dual-Core
  - M600: 2400 MHz – Turion II Ultra Dual-Core
  - M620: 2500 MHz – Turion II Ultra Dual-Core
  - M640: 2600 MHz – Turion II Ultra Dual-Core
  - M660: 2700 MHz – Turion II Ultra Dual-Core

Champlain (45 nm SOI)[edit]

Based on the AMD K10 microarchitecture
All models support: MMX, SSE, SSE2, SSE3, SSE4a, Enhanced 3DNow!, NX bit, AMD64, Cool'n'Quiet, AMD-V
Memory support: DDR3 SDRAM, DDR3L SDRAM

"Champlain" (45 nm, Dual-core)
Model number	Frequency	L2 cache	FPU width	HT	Multiplier¹	TDP	Socket	Release date	Order part number
Turion II P520	2.3 GHz	2 × 1 MB	128-bit	1.8 GHz	11.5×	25 W	Socket S1g4	May 12, 2010	TMP520SGR23GM
Turion II P540	2.4 GHz	2 × 1 MB	128-bit	1.8 GHz	12×	25 W	Socket S1g4	October 4, 2010	TMP540SGR23GM
Turion II P560	2.5 GHz	2 × 1 MB	128-bit	1.8 GHz	12.5×	25 W	Socket S1g4	October 19, 2010	TMP560SGR23GM
Turion II N530	2.5 GHz	2 × 1 MB	128-bit	1.8 GHz	12.5×	35 W	Socket S1g4	May 12, 2010	TMN530DCR23GM
Turion II N550	2.6 GHz	2 × 1 MB	128-bit	1.8 GHz	13×	35 W	Socket S1g4	October 4, 2010	TMN550DCR23GM

References[edit]

^ "The Inquirer report". The Inquirer. Archived from the original on February 10, 2007.{{cite web}}: CS1 maint: unfit URL (link)
^ "AMD Delivers Multi-Tasking Performance On-The-Go With First 64-Bit Dual-Core Mobile Processor". AMD. 2006-05-17. Archived from the original on 12 October 2008. Retrieved 2008-09-09.
^ AMD mobile CPU roadmap at Engadget
^ AnandTech review
^ PC Watch image
^ ^a ^b "The Inquirer report". The Inquirer. Archived from the original on July 5, 2007.{{cite web}}: CS1 maint: unfit URL (link)

External links[edit]

[1] "The Inquirer report". The Inquirer. Archived from the original on February 10, 2007.{{cite web}}: CS1 maint: unfit URL (link)

[2] "AMD Delivers Multi-Tasking Performance On-The-Go With First 64-Bit Dual-Core Mobile Processor". AMD. 2006-05-17. Archived from the original on 12 October 2008. Retrieved 2008-09-09.

[Engadget0-3] AMD mobile CPU roadmap at Engadget

[Anand0-4] AnandTech review

[5] PC Watch image

[Inquirer0-6] "The Inquirer report". The Inquirer. Archived from the original on July 5, 2007.{{cite web}}: CS1 maint: unfit URL (link)

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