Logo for the Zen microarchitecture
|Instruction set||AMD64 (x86-64)|
|CPUID code||Family 17h|
|L1 cache||64 KiB instruction, 32 KiB data per core|
|L2 cache||512 KiB per core|
|L3 cache||8 MiB per quad-core CCX|
|Transistors||14 nm (FinFET)|
|Predecessor||Excavator (4th gen)|
|Application||Desktop, Laptop, Server, Workstation|
|Product code name(s)||
Zen is the codename for a computer processor microarchitecture from AMD, and was first used with their Ryzen series of CPUs in February 2017. The first Zen based preview system was demonstrated at E3 2016, and first substantially detailed at an event hosted a block away from the Intel Developer Forum 2016. The first Zen-based CPUs codenamed "Summit Ridge" reached the market in early March 2017, Zen-derived Epyc server processors launched in June 2017 and Zen-based APUs arrived in November 2017.
Zen is a clean sheet design that differs from the long-standing Bulldozer architecture. Zen-based processors use a 14 nm FinFET process, are reportedly more energy efficient, and can execute significantly more instructions per cycle. SMT has been introduced, allowing each core to run 2 threads. The cache system has also been redesigned, making the L1 cache write-back. Zen processors use three different sockets: desktop and mobile Ryzen chips use the AM4 socket, bringing DDR4 support; the high-end desktop Zen-based Threadripper chips support quad-channel DDR4 RAM and offer 64 PCIe 3.0 lanes (vs 24 lanes), using the TR4 socket; and Epyc server processors offer 128 PCI 3.0 lanes and octal-channel DDR4 using the SP3 socket.
Zen is based on a SoC design. The memory, PCIe, SATA, and USB controllers are incorporated into the same chip as the processor cores. This has advantages in bandwidth and power, at the expense of chip complexity and die area. This SoC design will allow the Zen microarchitecture to scale from laptops and small-form factor mini PCs to high-end desktops and servers.
- 1 Design
- 2 History and development
- 3 Advantages over predecessors
- 4 Products
- 5 See also
- 6 References
- 7 External links
- L1 cache has been changed from write-through to write-back, allowing for lower latency and higher bandwidth
- SMT (simultaneous multithreading) architecture allows for 2 threads per core, a departure from the CMT (clustered multi-thread) design used in the previous Bulldozer architecture. This is a feature previously offered in some IBM, Intel and Oracle processors.
- A fundamental building block for all Zen-based CPUs is the Core Complex (CCX) consisting of four cores and their associated caches. Processor with more than four cores consist of multiple CCXs connected by Infinity Fabric.
- Four ALUs, two AGUs/load-store units, and two floating-point units per core.
- Newly introduced "large" micro-operation cache.
- Each SMT core can dispatch up to 6 micro-ops per cycle (a combination of 6 integer micro-ops and 4 floating point micro-ops per cycle)
- Close to 2× faster L1 and L2 bandwidth, total L3 cache bandwidth up 5×
- Clock gating
- Larger retire, load, and store queues
- Improved branch prediction using a hashed perceptron system with Indirect Target Array similar to the Bobcat microarchitecture, something that has been compared to a neural network by AMD engineer Mike Clark
- Branch predictor that is decoupled from the fetch stage
- Dedicated stack engine for modifying the stack pointer, similar to Intel Haswell and Broadwell processors
- Move elimination, a method that reduces physical data movement to reduce power consumption
- RDSEED support, a high-performance hardware random number generator instructions introduced in Intel's Broadwell microarchitecture
- Support for SMAP, SMEP, XSAVEC/XSAVES/XRSTORS, XSAVES, CLFLUSHOPT, CLZERO and ADCX instructions.
- AVX2 support
- ADX support.
- SHA support.
- PTE (page table entry) coalescing, which combines 4 kiB page tables into 32 kiB page size.
- Pure Power
- Smart Prefetch
- Precision Boost
- Extended Frequency Range (XFR), an automated overclocking feature which boosts clock speeds beyond the advertised turbo frequency.
|“||This is the first time in a very long time that we engineers have been given the total freedom to build a processor from scratch and do the best we can do. It is a multi-year project with a really large team. It's like a marathon effort with some sprints in the middle. The team is working very hard, but they can see the finish line. I guarantee that it will deliver a huge improvement in performance and power consumption over the previous generation.||”|
|— Suzanne Plummer, Zen team leader, on September 19th, 2015.|
The Zen architecture is built on a 14 nanometer FinFET process subcontracted to GlobalFoundries, giving greater efficiency than the 32 nm and 28 nm processes of previous AMD FX CPUs and AMD APUs, respectively. The "Summit Ridge" Zen family of CPUs use the AM4 socket and feature DDR4 support and a 95 W TDP (thermal design power). While newer roadmaps don't confirm the TDP for desktop products, they suggest a range for low-power mobile products with up to two Zen cores from 5 to 15 W and 15 to 35 W for performance-oriented mobile products with up to four Zen cores.
Each Zen core can decode four instructions per clock cycle and includes a micro-op cache which feeds two schedulers, one each for the integer and floating point segments. Each core has two address generation units, four integer units, and four floating point units. Two of the floating point units are adders, and two are multipliers. There are also improvements in the branch predictor. The L1 cache size is 64 KiB for instructions per core and 32 KiB for data per core. The L2 cache size 512 KiB per core, and the L3 is 1-2 MB per core. L3 caches offer 5x the bandwidth of previous AMD designs.
History and development
Zen was originally planned for 2017 following the ARM64-based K12 sister core, but on AMD's 2015 Financial Analyst Day it was revealed that K12 was delayed in favor of the Zen design, to allow it to enter the market within the 2016 timeframe, with the release of first Zen-based processors expected for October 2016.
In December 2015, it was rumored that Samsung may be contracted as a fabricator for AMD's 14 nm FinFET processors, including both Zen and AMD's then-upcoming Polaris GPU architecture. This was clarified by AMD's July 2016 announcement that products had been successfully produced on Samsung's 14 nm FinFET process. AMD stated Samsung would be used "if needed", arguing this would reduce risk for AMD by decreasing dependence on any one foundry.
Advantages over predecessors
Zen's from-scratch design is notably different from its predecessors, with many different types of changes and enhancements being made across the board in hopes of making Zen more competitive with Intel's architectures, and the software most often built with Intel's processor features in mind.
Processors built using Zen utilize 14 nm FinFET silicon. These processors are being produced at GlobalFoundries, though reports state some Zen processors may also be produced at TSMC. Prior to Zen, AMD's smallest process size was 28 nm, as utilized by their Steamroller and Excavator microarchitectures. The immediate competition, Intel's Skylake and Kaby Lake microarchitecture, are also fabricated on 14 nm FinFET; though Intel is planning to begin the release of 10 nm parts later in 2017. In comparison to Intel's 14 nm FinFET, AMD claimed in February 2017 the Zen cores would be 10% smaller. AMD also announced it would be using metal-insulator-metal process to increase the clock speeds and reduce voltages of its Zen products.
For identical designs, these die shrinks would use less current (and power) at the same frequency (or voltage). As CPUs are usually power limited (typically up to ~125 W, or ~45 W for mobile), smaller transistors allow for either lower power at the same frequency, or higher frequency at the same power.
One of Zen's major goals is to focus on performance per-core, and it is targeting a 40% improvement in instructions per cycle (IPC) over its predecessor. Excavator, in comparison, offered 4–15% improvement over previous architectures. AMD announced the final Zen microarchitecture actually achieved 52% improvement in IPC over Excavator. The inclusion of SMT also allows each core to process up to two threads, increasing processing throughput by better utilizing available resources.
The Zen processors also employ sensors across the chip to dynamically scale frequency and voltage. This allows for the maximum frequency to be dynamically and automatically defined by the processor itself based upon available cooling.
Pre-release reports stated APUs utilizing the Zen architecture would also support High Bandwidth Memory (HBM). However, the first demonstrated APU did not use HBM memory. Previous APUs from AMD relied on shared memory for both the GPU and the CPU.
Power consumption and heat output
Processors built at the 14 nm node on FinFET silicon should show reduced power consumption and therefore heat over their 28 nm and 32 nm non-FinFET predecessors (for equivalent designs), or be more computationally powerful at equivalent heat output/power consumption.
Zen is also expected to utilize clock gating, reducing the frequency of underutilized portions of the core to save power. This will be through AMD's SenseMI technology, using sensors across the chip to dynamically scale frequency and voltage.
Enhanced security and virtualization support
Zen added the support for AMD's Secure Memory Encryption (SME) and AMD's Secure Encrypted Virtualization (SEV). Secure Memory Encryption is real time memory encryption done per page table entry. This is done utilizing the onboard "Security" Processor (ARM Cortex-A5) at boot time to encrypt each page, allowing any DDR4 memory (including nonvolatile varieties) to be encrypted. AMD SME also makes the contents of the memory more resistant to memory snooping and cold boot attacks.
|“||SME can be used to mark individual pages of memory as encrypted through the page tables. A page of memory that is marked encrypted will be automatically decrypted when read from DRAM and will be automatically encrypted when written to DRAM. The SME feature is identified through a CPUID function and enabled through the SYSCFG MSR. Once enabled, page table entries will determine how the memory is accessed. If a page table entry has the memory encryption mask set, then that memory will be accessed as encrypted memory. The memory encryption mask (as well as other related information) is determined from settings returned through the same CPUID function that identifies the presence of the feature.||”|
The Secure Encrypted Virtualization (SEV) feature allows the memory contents of a virtual machine (VM) to be transparently encrypted with a key unique to the guest VM. The memory controller contains a high performance encryption engine which can be programmed with multiple keys for use by different VMs in the system. The programming and management of these keys is handled by the AMD Secure Processor firmware which exposes an API for these tasks. 
Incorporating much of a southbridge into the SoC, the Zen CPU includes SATA, USB, and PCI Express NVMe links. This can be augmented by available Socket AM4 chipsets which add connectivity options including additional SATA and USB connections, and support for AMD's Crossfire and Nvidia's SLI.
AMD, in announcing its Radeon Instinct line, argued that the upcoming Zen based Naples server CPU would be particularly suited for building deep learning systems. The expected 64 PCIe lanes per Naples CPU allows for 4 Instinct cards to connect at PCIe x16 to a single CPU. This compares favorably to the Intel Xeon line, with only 40 PCIe lanes.
The first desktop processors without graphics processing unit (codenamed "Summit Ridge") were initially expected to start selling at the end of 2016, according to an AMD roadmap; with the first mobile and desktop processors of the AMD Accelerated Processing Unit type (codenamed "Raven Ridge") following in late 2017. AMD officially delayed Zen until Q1 of 2017. In August 2016, an early demonstration of the architecture showed an 8 cores/16 threads engineering sample CPU at 3.0 GHz.
In December 2016, AMD officially announced the desktop CPU line under the Ryzen brand for release in Q1 2017. It also confirmed Server processors would be released in Q2 2017, and mobile APUs in H2 2017.
On March 2, 2017, AMD officially launched the first Zen architecture-based octacore Ryzen desktop CPUs. The final clock speeds and TDPs for the 3 CPUs released in Q1 of 2017 demonstrated a significantly better performance-per-watt benefits over the last generation K15h (Piledriver) architecture. The octacore Ryzen desktop CPUs demonstrated performance-per-watt comparable to Intel's Broadwell architecture based octacore CPUs.
In March 2017, AMD also demonstrated an engineering sample of the unreleased server CPU based on Zen architecture. The CPU (codenamed "Naples") was configured as a dual socket server platform with each CPU having 32 cores/64 threads.
Branding & Model
|Clock rate (GHz)||Cache[a]||TDP||Socket||Memory
|High-End (HEDT)||16 (32)||Ryzen
per core 
|32 MB ||180 W||TR4||DDR4-2666
|64||Aug 10, 2017||$999|
|8 (16)||1900X||3.8||16 MB||Aug 31, 2017||$549|
|Performance||8 (16)||Ryzen 7||1800X||3.6||4.0||4.1||512 KB
|16 MB||95 W||AM4||DDR4-2666
|24||Mar 2, 2017||$499|
|Pro 1700X||TBA||Jun 29, 2017||TBA|
|1700||3.0||3.7||3.75||65 W||Mar 2, 2017||$329|
|Pro 1700||TBA||Jun 29, 2017||TBA|
|Mainstream||6 (12)||Ryzen 5||1600X||3.6||4.0||4.1||512 KB
|16 MB||95 W||AM4||DDR4-2666
|24||Apr 11, 2017||$249|
|Pro 1600||TBA||Jun 29, 2017||TBA|
|4 (8)||1500X||3.5||3.7||3.9||Apr 11, 2017||$189|
|Pro 1500||TBA||Jun 29, 2017||TBA|
|1400||3.2||3.4||3.45||8 MB||Apr 11, 2017||$169|
|Entry-Level||4 (4)||Ryzen 3||1300X||3.5||3.7||3.9||512 KB
|8 MB||65 W ||AM4||DDR4-2666
|24||Jul 27, 2017||$129|
|Pro 1300||TBA||Jun 29, 2017||TBA|
|1200||3.1||3.4||3.45||Jul 27, 2017||$109|
|Pro 1200||TBA||Jun 29, 2017||TBA|
|APU Branding & Model||CPU||GPU||TDP||Memory
|Clock rate (GHz)||Cache[a]||Model||Cores||Config[b]||Clock||Processing power (GFLOPS)[c][d]|
|Ultrathin||Ryzen 5 2500U||4 (8)||2.0||3.6||Unknown||2 MB||4 MB||Vega 8||8||512:32:?||1100||1126.4||15 W (configurable 12-25 W)||DDR4-2400 (Dual channel)||26 October 2017|
|Ultrathin||Ryzen 7 2700U||2.2||3.8||Unknown||Vega 10||10||640:40:?||1300||1664|
AMD announced in March 2017 it will release a server platform based on Zen, codenamed Naples, in the second quarter of the year. The platform will include 1 and 2 socket systems. The CPUs in multi processor configurations will communicate via AMD's Infinity Fabric. Each chip supports 8 channels of memory and 128 PCIe 3.0 lanes, of which 64 lanes will be used for CPU to CPU communication through Infinity Fabric when installed in a dual processor configuration. AMD officially revealed Naples under the brand name Epyc in May 2017.
On June 20 2017, AMD officially released the Epyc 7000 series CPUs at a launch event in Austin, Texas.
|Brand & Model||Cores
|Clock rate (GHz)||Cache||Memory||TDP
|2P||Epyc||7601||32 (64)||2.2||2.7||3.2||32 x 512||64||8||DDR4-2666||180||SP3 LGA
|7551||2.0||2.55||3.0||32 x 512||$3400+|
|7501||2.6||32 x 512||155/170||$3400|
|7451||24 (48)||2.3||2.9||3.2||24 x 512||180||$2400+|
|7401||2.0||2.8||3.0||24 x 512||155/170||$1850|
|7351||16 (32)||2.4||2.9||16 x 512||155/170||$1100+|
|7301||2.2||2.7||16 x 512||$800+|
|7281||2.1||16 x 512||32||$650|
|7251||8 (16)||2.9||8 x 512||DDR4-2400||120||$475|
|1P||7551P||32 (64)||2.0||2.55||3.0||32 x 512||64||DDR4-2666||180||$2100|
|7401P ||24 (48)||2.8||24 x 512||155/170||$1075|
|7351P ||16 (32)||2.4||2.9||16 x 512||$750|
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- Ryzen Processors - AMD