File:5 Stage Pipeline.svg

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Description
English: A diagram showing the stage of execution reached by five consecutive instructions in a 5-stage microprocessor. At clock cycle 4, the 1st instruction is in the "memory access" phase, the second is in the "execute" phase, the third in the "instruction decode" phase, the fourth in the "instruction fetch" phase and the fifth hasn't been fetched yet.
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Source Own work
Author Inductiveload
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inception

22 January 2009

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image/svg+xml

checksum

0a9f81f80243ffb09e2c7d660fb9cd67b8245401

determination method: SHA-1

data size

34,001 byte

height

190 pixel

width

300 pixel

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Date/TimeThumbnailDimensionsUserComment
current18:24, 22 January 2009Thumbnail for version as of 18:24, 22 January 2009300 × 190 (33 KB)Inductiveload{{Information |Description={{en|1=A diagram showing the stage of execution reached by five consecutive instructions in a 5-stage microprocessor. At clock cycle 4, the 1st instruction is in the "memory access" phase, the second is in the "execute" phase, t
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