File:Logic block pins.svg
Size of this PNG preview of this SVG file: 205 × 185 pixels. Other resolutions: 266 × 240 pixels | 532 × 480 pixels | 851 × 768 pixels | 1,135 × 1,024 pixels | 2,269 × 2,048 pixels.
Original file (SVG file, nominally 205 × 185 pixels, file size: 6 KB)
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Summary
An example of the connections of an FPGA logic block.
Source
Created by User:Joelholdsworth in Inkscape. This image is inelligable for copyright.
This W3C-unspecified vector image was created with Inkscape .
Licensing
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This work is ineligible for copyright and therefore in the public domain because it consists entirely of information that is common property and contains no original authorship. |
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 16:39, 1 March 2007 | | 205 × 185 (6 KB) | Joelholdsworth~commonswiki | ==Summary== An example of the connections of an FPGA logic block. ==Source== Created by User:Joelholdsworth in Inkscape. Use of this work which I have created is allowed under the terms of the GFDL license. {{Created with Inkscape}} ==License== {{GFD |
| 16:35, 1 March 2007 |  | 205 × 185 (6 KB) | Joelholdsworth~commonswiki | ==Summary== An example of the connections of an FPGA logic block. ==Source== Created by User:Joelholdsworth in Inkscape. Use of this work which I have created is allowed under the terms of the GFDL license. {{Created with Inkscape}} ==License== {{ |
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