Joint Test Action Group

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Joint Test Action Group (JTAG) is the common name used for the IEEE 1149.1 standard entitled Standard Test Access Port and Boundary-Scan Architecture for test access ports used for testing printed circuit boards using boundary scan. JTAG is often used as an IC debug or probing port.

Contents 1 History 2 Electrical characteristics 3 Test pins 4 Common extensions 5 Widespread uses 6 Client Support 6.1 JTAG Adapter Hardware 7 See also 8 References 9 External links

[edit] History

JTAG was an industry group formed in 1985 to develop a method to test populated circuit boards after manufacture. At the time, multi-layer boards and non-lead-frame ICs were becoming standard and making connections between ICs not available to probes. The majority of manufacturing and field faults in circuit boards were due to solder joints on the boards, imperfections in board connections, or the bonds and bond wires from IC pads to pin lead frames. JTAG was meant to provide a pins-out view from one IC pad to another so all these faults could be discovered. The industry standard finally became an IEEE standard in 1990 as IEEE Std. 1149.1-1990 after many years of initial use. That same year Intel released the first processor with JTAG: the 80486 which led to quicker industry adoption by all manufacturers. In 1994, a supplement that contains a description of the boundary scan description language (BSDL) was added. Since then, this standard has been adopted by electronics companies all over the world. Boundary-scan is nowadays mostly synonymous with JTAG.

Although it was originally designed for testing printed circuit board assemblies, today JTAG is also used for accessing sub-blocks of integrated circuits, making it a useful mechanism for debugging embedded systems, providing a convenient "back door" into the system. When used as a debugging tool, an in-circuit emulator - which in turn uses JTAG as the transport mechanism - enables a programmer to access an on-chip debug module which is integrated into the CPU, via the JTAG interface. The debug module enables the programmer to debug the software of an embedded system.

Besides debugging, another purpose of the JTAG interface is allowing device programmer hardware to transfer data into internal non-volatile device memory (CPLDs). Some device programmers serve a double purpose for programming as well as debugging the device. In the case of FPGAs, volatile memory devices, they can also be programmed via the JTAG port normally during development work. In addition newer parts, for instance Xilinx Virtex5, have internal monitoring capability (temperature, voltage and current) accesible via the JTAG port.

In many ICs today, internal registers are linked together in sets called scan chains. By externally manipulating the scan chains it is possible to test the combinational logic in the IC after it is mounted on the circuit card and possibly while in a functioning system. When combined with built-in self-test (BIST), the JTAG scan chain enables a low overhead, embedded solution to testing an IC for certain static faults (shorts, opens, and logic errors). The scan chain mechanism does not generally help diagnose or test for timing, temperature or other dynamic operational errors that may occur.

[edit] Electrical characteristics

A JTAG interface is a special four/five-pin interface added to a chip, designed so that multiple chips on a board can have their JTAG lines daisy-chained together if specific conditions are met^[1], and a test probe need only connect to a single "JTAG port" to have access to all chips on a circuit board. The connector pins are

1. TDI (Test Data In)
2. TDO (Test Data Out)
3. TCK (Test Clock)
4. TMS (Test Mode Select)
5. TRST (Test Reset) optional.

Test reset signal is not shown in the image.

Since only one data line is available, the protocol is necessarily serial. The clock input is at the TCK pin. Configuration is performed by manipulating a state machine one bit at a time through a TMS pin. One bit of data is transferred in and out per TCK clock pulse at the TDI and TDO pins, respectively. Different instruction modes can be loaded to read the chip ID, sample input pins, drive (or float) output pins, manipulate chip functions, or bypass (pipe TDI to TDO to logically shorten chains of multiple chips). The operating frequency of TCK varies depending on all chips in the chain (lowest speed must be used), but it is typically 10-100 MHz (100-10 ns per bit).

The TRST pin is an optional active-low reset to the test logic - usually asynchronous, but sometimes synchronous, depending on the chip. If the pin is not available, the test logic can be reset by clocking in a reset instruction synchronously.

Data presented to TDI must be valid for some chip-specific Setup time before and Hold time after the rising edge of TCK. TDO data is valid for some chip-specific time after the falling edge of TCK. This can be seen e.g. with the JTAG timing diagram of the DS4550 chip (http://pdfserv.maxim-ic.com/en/ds/DS4550.pdf).

Even though few consumer products provide an explicit JTAG port connector, the connections are very often available on the printed circuit board as a remnant from development prototyping and/or production. When exploited, these connections often provide an excellent means for reverse engineering.

[edit] Test pins

Devices communicate to the world via a set of input and output pins. By themselves, these pins provide limited visibility into the workings of the device. However, devices that support boundary scan contain a shift-register cell for each signal pin of the device. These registers are connected in a dedicated path around the device's boundary (hence the name). The path creates a virtual access capability that circumvents the normal inputs and provides direct control of the device and detailed visibility at its outputs.^[2]

During testing, I/O signals enter and leave the chip through the boundary-scan cells. The boundary-scan cells can be configured to support external testing for interconnection between chips (EXTEST) or internal testing for logic within the chip (INTEST).

To provide the boundary scan capability, IC vendors add additional logic to each of their devices, including scan cells for each of the signal pins, these cells are then connected together to form the data register (DR), four or five additional pins, and control circuitry. The overhead for this additional logic is minimal and generally well worth the price to have efficient testing at the board level.

[edit] Common extensions

Manufacturer's extensions: Infineon, MIPS EJTAG, Freescale COP and OnCE, etc.

ARM has an extensive debug architecture that started with EmbeddedICE (a debug facility available on most ARM cores), and now includes many additional components such as an ETM (Embedded Trace Macrocell) with a high speed trace port.

Nexus defines a processor debug infrastructure. One of its hardware interfaces is JTAG. It also defines a high speed auxiliary port interface, used for tracing and more. Nexus is used with some newer platforms, such as the Atmel AVR32 and Freescale MPC5500 series processors.

[edit] Widespread uses

• A large proportion of high end embedded systems have a JTAG port. ARM Architecture processors come with JTAG support, as do most FPGAs. Modern 8-bit and 16-bit Microcontroller chips, such as Atmel AVR and TI MSP430 chips, rely on JTAG to support in-circuit debugging and firmware reprogramming (except on the very smallest chips, which don't have enough pins to spare and thus tend to rely on proprietary single-wire programming interfaces).
• The PCI bus connector standard contains optional JTAG signals on pins 1-5^[3]; PCI-Express contains JTAG signals on pins 5-9^[4]. A special JTAG card can be used to reflash a corrupt BIOS.
• Almost all FPGAs and CPLDs used today can be programmed via the JTAG port.

[edit] Client Support

The target's JTAG interface is accessed using some JTAG-enabled application and some JTAG adapter hardware. There is a wide range of such hardware, optimized for purposes such as production testing, debugging high speed systems, low cost microcontroller development, and so on. In the same way, the software used to drive such hardware can be quite varied. Software developers mostly use JTAG for debugging and updating firmware.

[edit] JTAG Adapter Hardware

There are no official standards for JTAG adapter physical connectors, if space allows most designers opt for standard 2.54mm (0.1 inch) pin headers (surface mounted), if space is tight then adaptor cables are used to connect whatever is fitted to the board and interface it to the appropriate manufacturer pinout.

Most common JTAG pinouts are ^[5]:

• ARM 2x7 or 2x10 pin, used by almost all ARM based systems
• MIPS EJTAG (2x7 pin) used for MIPS based systems
• 2x5 pin Altera ByteBlaster-compatible JTAG extended by many vendors
• 2x5 pin AVR extends Altera JTAG with SRST (and in some cases TRST and an event output)
• 2x7 pin Texas Instruments used with DSPs and ARM-based products such as OMAP
• 8pin (single row) generic PLD JTAG compatible with many Lattice ispDOWNLOAD cables

Those connectors tend to include more than just the four standardized signals (TMS, TCK, TDI, TDO). Usually reset signals are provided, one or both of TRST (TAP reset) and SRST (system reset). The board voltage is usually provided, so that JTAG adapters can level-shift their inputs and outputs; that may also serve as a "board present" debugger input. Event input or output signals may be provided, or general purpose I/O (GPIO) lines, to support more complex debugging architectures.

Higher end products frequently use dense connectors (frequently 38-pin Mictor connectors) to support high-speed tracing in conjunction with JTAG operations. A recent trend is to have development boards integrate a USB interface to JTAG. Production boards often rely on bed-of-nails connections for testing and programming.

If you want to acquire a JTAG adapter, you first need to decide what systems it must support. Everything else follows from that, including your software options. Low-end adapters may cost less than $US 50 and have limited hardware and software support. High-end adapters can cost a hundred times as much, including software support, and have corresponding improvements in capability.

[edit] See also

• Boundary scan test
• Boundary scan description language
• AOI Automated optical inspection
• AXI Automated x-ray inspection
• ICT In-circuit test
• Functional testing (see Acceptance testing)
• Nexus 5001
• Background Debug Mode interface

[edit] References

[edit] External links

This article's external links may not follow Wikipedia's content policies or guidelines. Please improve this article by removing excessive or inappropriate external links.

• JTAG/Boundary-scan explained Knowledge base plus industry links
• JTAG - what can it do for you? Application and cost purposes
• TI JTAG Primer
• JTAG Tutorial and Boundary-Scan Applications
• JTAG FAQ
• Free JTAG Resources
• Free verilog JTAG TAP controller and Boundary Scan configurator
• Overview of JTAG technology - Design for Testability (DFT) Guidelines, BGA, ISP; Chain Integrity, Connection & Functional Testing
• Brief technical guide to JTAG Boundary Scan - An overview of how JTAG is implemented. Signals, TAP controller, Registers, Instructions.
• A Brief Introduction to the JTAG Boundary Scan Interface
• A detailed non-commercial discussion of JTAG Includes state diagrams etc.
• Debugging with JTAG (CELF presentation)