List of Intel CPU microarchitectures
||Pipeline stages||max. Clock||Tech process|
|1989||486 (80486)||3||100 MHz||1 µm|
|1993||P5 (Pentium)||5||300 MHz||0.6 µm|
|1995||P6 (Pentium Pro;
later Pentium II)
|14 (17 with load & store/
||450 MHz||350 nm|
|1999||P6 (Pentium III)
|12 (15 with load & store/retire)||
(Pentium 4)(Willamette) and (Northwood)
|20 unified with branch prediction||
|2003||Pentium M||10 (12 with fetch/
|31 unified with branch prediction||3800 MHz||90 nm|
|2006||Intel Core||12 (14 with fetch/retire)||3333 MHz||65 nm|
|2008||Nehalem||20 unified (14 without miss prediction)||3600 MHz||45 nm|
|2008||Bonnell||16 (20 with prediction miss)||2100 MHz||32 nm|
|2010||Westmere||20 unified (14 without miss prediction)||3730 MHz|
|2011||Sandy Bridge||14 (16 with fetch/retire)||4000 MHz|
|2012||Ivy Bridge||14 (16 with fetch/retire)||4100 MHz||22 nm|
|2013||Silvermont||14-17 (16-19 with fetch/retire)||2670 MHz|
|2013||Haswell||14 (16 with fetch/retire)||4400 MHz|
|2014||Broadwell||14 (16 with fetch/retire)||3700 MHz||14 nm|
|2015||Skylake||14 (16 with fetch/retire)||4200 MHz|
|2016||Goldmont||20 unified with branch prediction||2600 MHz|
|2016||Kaby Lake||14 (16 with fetch/retire)||4500 MHz|
|2017||Coffee Lake||14 (16 with fetch/retire)||4800 MHz|
|2017||Goldmont Plus||? 20 unified with branch prediction ?||2800 MHz|
|14||? MHz||10 nm|
- Before P5
- 8086: first x86 processor; initially a temporary substitute for the iAPX 432 to compete with Motorola, Zilog, and National Semiconductor and to top the successful Z80.
- 186: included a DMA controller, interrupt controller, timers, and chip select logic. A small number of additional instructions.
- 286: first x86 processor with protected mode including segmentation based virtual memory management. Performance improved by a factor of 3...4 over 8086. Included instructions relating to protected mode.
- i386: first 32-bit x86 processor. Introduced paging on top of segmentation which is the most commonly used memory protection technology in modern operating systems ever since. Many additional powerful and valuable new instructions.
- i486: Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining. Faster per MHz than the 386. Small number of new instructions.
- original Pentium microprocessors, first x86 processor with super-scalar architecture, branch prediction and RISC µop decode scheme.
- used in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. First x86 processor to support SIMD instruction with XMM register implemented, integrated register renaming and out-of-order execution. Some important new instructions, including conditional moves, which allow the avoidance of costly branch instructions. Added 36-bit physical memory addressing, "Physical Address Extension (PAE)".
- Commonly referred to as P7 although its internal name was P68 (P7 was used for Itanium). Used in Pentium 4, Pentium D, and some Xeon microprocessors. Very long pipeline. The Prescott was a major architectural revision. Later revisions were the first to feature Intel's x86-64 architecture, enhanced branch prediction and trace cache, and eventually support was added for the NX (No eXecute) bit to implement executable-space protection.
- Pentium M
- updated version of Pentium III's P6 microarchitecture designed from the ground up for mobile computing and first x86 to support micro-op fusion and smart cache.
- Intel Core
- reengineered P6-based microarchitecture used in Core 2 and Xeon microprocessors, built on a 65 nm process, supporting x86-64 level SSE instruction and macro-op fusion and enhanced micro-op fusion with a wider front end and decoder, larger out-of-order core and renamed register, support loop stream detector and large shadow register file.
- released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die. Added important powerful new instructions, SSE4.2.
- Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features.
- 45 nm, low-power, in-order microarchitecture for use in Atom processors.
- Saltwell: 32 nm shrink of the Bonnell microarchitecture.
- Larrabee (cancelled 2010)
- multi-core in-order x86-64 updated version of P5 microarchitecture, with wide SIMD vector units and texture sampling hardware for use in graphics. Cores derived from this microarchitecture are called MIC (Many Integrated Core).
- Sandy Bridge
- released January 9, 2011, built on a 32 nm process and used in the Core i7, Core i5, Core i3 second generation microprocessors, and in Pentium B9XX and Celeron B8XX series. Formerly called Gesher but renamed in 2007. First x86 to introduce 256 bit AVX instruction set and implementation of YMM register.
- Ivy Bridge: 22 nm shrink of the Sandy Bridge microarchitecture released April 28, 2012.
- 22 nm, out-of-order microarchitecture for use in Atom processors, released May 6, 2013.
- Airmont: 14 nm shrink of the Silvermont microarchitecture.
- 22 nm microarchitecture, released June 3, 2013. Added a number of important powerful new instructions, including FMA.
- Broadwell: 14 nm shrink of the Haswell microarchitecture, released in September 2014. Formerly called Rockwell.
- new 14 nm microarchitecture, released August 5, 2015.
- Kaby Lake: successor to Skylake, broke Intel's Tick-Tock schedule due to delays with the 10 nm process.
- Coffee Lake: successor to Kaby Lake and a second refinement to the 14 nm process
- Cascade Lake: successor to Kaby Lake-X
- Cannonlake: expected in 2018. It will be a 10 nm shrink of Kaby Lake. Formerly called Skymont.
- 14 nm Atom microarchitecture iteration after Silvermont but borrows heavily from Skylake processors (e.g., GPU), released April 2016.
- Goldmont Plus: successor to Goldmont microarchitecture, still based on the 14 nm process, released December 11, 2017.
- Ice Lake
- new 10 nm microarchitecture, expected in 2018 / 2019.
- Tiger Lake: an update of Ice Lake, expected in 2019.
- original Itanium microarchitecture. Used only in the first Itanium microprocessors.
- enhanced microarchitecture used in the first two generations of the Itanium 2 microprocessor.
- enhanced McKinley microarchitecture used in the Itanium 2 9000- and 9100-series of processors. Added dual core, coarse multithreading, and other improvements.
- enhanced microarchitecture used in the Itanium 9300 series of processors. Added quad core, SMT, an integrated memory controller, QuickPath Interconnect, and other improvements.
- Itanium processor featuring a new microarchitecture.
- the last Itanium microarchitecture. It has slightly higher clock speed than Poulson.
Pentium 4 / Core Lines
|Pentium 4 / Core Roadmap|
Mobile Pentium 4
|–||Sandy Bridge-EP||Sandy Bridge-E||Sandy Bridge||Sandy Bridge-M|
|22 nm||Ivy Bridge
|Ivy Bridge||Ivy Bridge-M|
|Haswell-MB (37–57W TDP, PGA package)|
Haswell-H (47W TDP, BGA package)
Haswell-ULP/ULX (11.5–15W TDP)
|Broadwell-E||Broadwell-DT||Broadwell-H (37–47W TDP)|
Broadwell-U (15–28W TDP)
Broadwell-Y (4.5W TDP)
|Skylake-X ||Skylake-S||Skylake-H (35–45W TDP)|
Skylake-U (15–28W TDP)
Skylake-Y (4.5W TDP)
|Kaby Lake-S||Kaby Lake-H (35–45W TDP)|
Kaby Lake-U (15–28W TDP)
Kaby Lake-Y (4.5W TDP)
|10 nm||Cannon Lake
|Ice Lake||2018 / 2019|
|Tiger Lake||2019 / 2020|
|45 nm||Bonnell||2008||Silverthorne||N/A||Diamondville||Tunnel Creek,
|32 nm||Saltwell||2011||Medfield (Penwell & Lexington),
Clover Trail+ (Cloverview)
|Clover Trail (Cloverview)||Cedar Trail (Cedarview)||Unknown||Centerton & Briarwood||Unknown||Berryville|
|22 nm||Silvermont||2013||Merrifield (Tangier) , Slayton,
|14 nm||Airmont||2014||Binghamton & Riverton||Cherry Trail-T (Cherryview) ||Braswell ||Denverton Cancelled||Unknown||Unknown|
|2016||Broxton Cancelled||Willow Trail Cancelled
|Apollo Lake ||Denverton ||Unknown||Unknown|
|10 nm||Tremont||Unknown||Unknown||Unknown||Mercury Lake||Unknown||Unknown||Unknown|
- List of Intel microprocessors - Consumer Computer or non-consumer workstation
- List of AMD CPU microarchitectures
- Marvell Technology Group XScale microarchitecture
- "An Update On Our Graphics-related Programs". May 25, 2010.
- "Intel Software Development Emulator".
- ""Goldmont"- the sequel to Silvermont Atom?".
- Anton Shilov (June 19, 2007). "Intel Plans to change Itanium Micro-Architecture". X-bit Labs. Archived from the original on October 5, 2007. Retrieved 2007-10-05.
- Crothers, Brooke (2009-02-10). "Intel moves up rollout of new chips | Nanotech - The Circuits Blog - CNET News". News.cnet.com. Retrieved 2014-02-25.
- "Intel CEO: Latest Platforms, Processors Form New Foundations For Digital Entertainment And Wireless Computing".
- "Intel Unveils World's Best Processor".
- "Intel Unveils 16 Next-Generation Processors, Including First Notebook Chips Built on 45nm Technology".
- "Intel Launches Fastest Processor on the Planet". www.intel.com.
- Mark Bohr (Intel Senior Fellow, Logic Technology Development) (2009-02-10). "Intel 32nm Technology" (PDF).
- "Intel - Data Center Solutions, IoT, and PC Innovation". Intel.
- "Intel Sandy Bridge chip coming January 5".
- Pop, Sebastian. "Intel Ivy Bridge CPU Range Complete by Next Year".
- "22nm technology. May 2011" (PDF).
- "Ivy Bridge EP and EX coming up in a year's time - the multi-socket platform heaven". 9 April 2012.
- "Ivy Bridge-E delayed until second half of 2013".
- "Leaked specifications of Haswell GT1/GT2/GT3 IGP". Tech News Pedia. 2012-05-20. Retrieved 2014-02-25.
- "Devils Canyon mit bis zu 4,4 GHz, ohne verlöteten Deckel". golem.de. Jun 3, 2014.
- "After Intel's Haswell comes Broadwell, Sk……". 31 March 2011.
- "Intel to release 22-core Xeon E5 v4 "Broadwell-EP" late in 2015 - KitGuru". www.kitguru.net.
- "The wait for Skylake is almost over, first desktop chips likely to hit August 5". 6 July 2015.
- Windeck, Christof. "Intel Xeon Gold, Platinum: Skylake-SP für Server "Mitte Sommer"". heise.de. Retrieved 2 May 2017.
- Mujtaba, Hassan. "Intel X299 HEDT Platform For Skylake X and Kaby Lake X Processors Announcement on 30th May, Launch on 26th June – Reviews Go Live on 16th June". wccftech.com. Retrieved 2 May 2017.
- "Intel confirms tick-tock shattering Kaby Lake processor as Moore's Law falters". ArsTechnica.com. Jul 15, 2015.
the switch to 10nm manufacturing has been delayed until the second half of 2017.
- "Coffee Lake: Intels 6C-Prozessoren erfordern neue Boards - Golem.de".
- "Intel currently developing 14nm, aiming towards 5nm chips - CPU - News". HEXUS.net. 2012-05-15. Retrieved 2014-02-25.
- "Intel's next generation chip plans: Ice Lake and a slow 10nm transition".
- "Intel's Cannonlake CPUs To Be Succeeded By 10nm Ice Lake Family in 2018 and 10nm Tiger Lake Family in 2019". WCCFTech. 2016-01-20.
- Eassa, Ashraf. "What's the Name of Intel's Third 10-Nanometer Chip?".
- Eassa, Ashraf. "Here's When Intel Corporation Could Launch the "Ice Lake" Family of Processors".
- "Intel's Silvermont Architecture Revealed: Getting Serious About Mobile". AnandTech.
- Hiroshige, Goto. "Intel Products for Tablets & SmartPhones" (PDF). 標準. Impress. Archived from the original (PDF) on 2013-11-14.
- "Import Data and Price of anniedale".
- "Products (Formerly Braswell)". Intel® ARK (Product Specs). Retrieved 5 April 2016.
- Smith, Ryan; Cutress, Ian (29 April 2016). "Intel's Changing Future: Smartphone SoCs Broxton & SoFIA Officially Canceled". Anandtech.com. Retrieved 29 June 2016.
- "Products (Formerly Apollo Lake)". Intel® ARK (Product Specs). Retrieved 6 January 2016.
- "Products (Formerly Denverton)". Intel® ARK (Product Specs). Retrieved 6 January 2016.
- Wan, Samuel (2 June 2017). "Intel Gemini Lake SoC Leaked and Detailed". eTeknix.com. Retrieved 2 June 2017.