Memory buffer register
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A memory buffer register (MBR) or memory data register (MDR) is the register in a computer's processor, or central processing unit, CPU, that stores the data being transferred to and from the immediate access storage. It contains the copy of designated memory locations specified by the memory address register. It acts as a buffer allowing the processor and memory units to act independently without being affected by minor differences in operation. A data item will be copied to the MBR ready for use at the next clock cycle, when it can be either used by the processor for reading or writing or stored in main memory after being written.
which are to be transferred from memory to other components or vice versa. A word to be stored must be transferred to the MBR, from where it goes to the specific memory location, and the arithmetic data to be processed in the ALU first goes to MBR and then to accumulated register, and then it is processed in the ALU.
The MDR is a two-way register. When data is fetched from memory and placed into the MDR, it is written to go in one direction. When there is a write instruction, the data to be written is placed into the MDR from another CPU register, which then puts the data into memory.
Far more complex memory interfaces exist, but this is the simplest that can work.
The Memory Data Register (MDR) contains the data value being fetched or stored. It is a common mistake to say that the MDR should be W bits wide, where W is the cell size. However, on most computers the cell size is only 8-bits, and most data values occupy multiple cells. Thus, the size of the MDR is usually a multiple of 8 bits. Typical values of MDR width are 32 and 64 bits, which would allow us to fetch, in a single step, either an integer or a float value.
For example, to retrieve the contents of cell 123, we would load the value 123 (in binary) into the MAR and perform a fetch operation. When the operation is done, a copy of the contents of cell 123 would be in the MDR. To store the value 98 into cell 4, we load a 4 into the MAR and a 98 into the MDR and perform a store. When the operation has completed the contents of cell 4 will have been set to 98, by discarding whatever was there previously.
The MDR has two inputs and two outputs; data may be loaded into the MDR either from the memory bus or from the internal processor bus. The data stored in the MDR may be outputted onto either bus.
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