PDP-11

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The PDP-11 was a series of 16-bit minicomputers sold by Digital Equipment Corp. from 1970^[1][2] into the 1990s^[2]. The PDP-11 was a successor to DEC's PDP-8 computer in the PDP series of computers. It had several uniquely innovative features, and was easier to program than its predecessors. It was well-liked by programmers, and it was replaced in the mid-range minicomputer niche by the VAX-11 32-bit extension of the PDP-11. Much of the market for both machines would be taken by personal computers, including the IBM PC and Apple II, and workstations, such as those from Sun Microsystems.

Contents 1 Unique features of the PDP-11 Series 1.1 Orthogonality 1.2 No dedicated I/O bus 1.3 Interrupts 1.4 Designed for mass production 2 The LSI-11 3 The decline of the PDP-11 4 PDP-11 lore 5 Architectural details 5.1 Memory management 5.1.1 Memory expansion 5.1.2 Data formats 5.2 Addressing modes 5.2.1 General register addressing modes 5.2.2 Program counter addressing modes 5.2.3 Stack addressing modes 5.3 Instruction set 5.3.1 Double-operand instructions 5.3.2 Single-operand instructions 5.3.3 Program Control instructions 5.3.4 Jump & Subroutine instructions 5.3.5 Miscellaneous instructions 5.3.6 Condition Code operations 5.3.7 "Extended Instruction Set" (EIS) 5.3.8 "Floating Instruction Set" (FIS) 5.3.9 "Floating Point Processor" (FPP) 5.3.10 "Commercial Instruction Set" (CIS) 5.3.11 Inconsistent instructions 5.4 Interrupts 6 MACRO-11 assembly language 7 PDP-11 models 7.1 Unibus models 7.2 Q-bus models 7.3 Models without standard bus 7.4 Models that were planned but never introduced 7.5 Special purpose versions 7.6 Unauthorized clones 8 Operating systems 9 See also 10 Notes 11 References 12 Further reading 13 External links

[edit] Unique features of the PDP-11 Series

[edit] Orthogonality

The PDP-11 instruction set was mostly orthogonal. For example, instead of instructions such as Load and Store, the PDP-11 had a Move instruction for which either operand (source and destination) could be memory or register. There were no Input or Output instructions; each device responded to a memory location and so the same Move was used instead; orthogonality would even let you move data directly from an input device to an output device. More complex instructions such as Add likewise adapted to having memory, register, input, or output as source or destination. (These days, a development environment could give a programmer the illusion of orthogonality on any machine; but back then, programmers occasionally needed to understand the operation of the hardware.)

Generally, any operand could apply any of eight addressing modes to eight registers. The addressing modes provided register, immediate, absolute, relative, deferred (indirect), and indexed addressing, and could specify autoincrementation and autodecrementation of a register. (Whether such adjustment is by 1 or by 2 is the most complex rule of the language, but totally regular and sensible in every case.) Use of relative addressing let a machine-language program be position-independent.

For these reasons, PDP-11 programmers viewed the assembly language as easy to learn and uniquely elegant.

This article provides more details on the addressing modes and instruction set.

[edit] No dedicated I/O bus

In the most radical departure from earlier computers, the initial models of the PDP-11 had no dedicated bus for input/output; it had only a memory bus called the Unibus. All input and output devices were mapped to memory addresses, so no special I/O instructions were needed.

An input/output device determined the memory addresses to which it would respond and the interrupt priority it would request, and specified its own interrupt vector. This loose framework provided by the processor architecture made it unusually easy to invent new bus devices, including devices to control hardware that had not been contemplated when the processor was designed.

Higher-performance members of the PDP-11 family, starting with the PDP-11/45, departed from the single bus approach. Instead, memory was interfaced by dedicated circuitry and space in the CPU cabinet, while the Unibus continued to be used for I/O only. In the PDP-11/70 this was taken a step further, with the addition of a dedicated interface from disks and tapes, via the Massbus to memory. Use of different buses was not visible to the programmer, however, and the orthogonality of the assembly language was preserved.

[edit] Interrupts

The PDP-11 supported hardware interrupts at four priority levels. Interrupts were serviced by software service routines, which could specify whether they themselves could be interrupted (achieving interrupt nesting). The event that caused the interrupt was indicated by the device itself, as it informed the processor of the address of its own service routine.

This article provides more details on interrupts.

[edit] Designed for mass production

Finally, the PDP-11 was designed to be produced in a factory by semiskilled labor. All of the dimensions of its pieces were relatively non-critical. It used a wire-wrapped backplane. That is, the printed circuit boards plugged into a backplane connector. The backplane connectors had square pins that could be connected to by wrapping wires around them. The corners of the pins would bite into the wire to form a gas-tight (i.e. corrosion-proof, therefore reliable) connection.

[edit] The LSI-11

The LSI-11 (PDP-11/03) was the first PDP-11 model produced using large-scale integration; the entire CPU was contained on 4 LSI chips made by Western Digital (the MCP-1600 chip set). It used a bus which was a close variant of the Unibus called the Q-Bus; it differed from the Unibus primarily in that addresses and data were multiplexed onto a shared set of wires, as opposed to having separate sets of wires, as in the Unibus. It also differed slightly in how it addressed I/O devices and it eventually allowed a 22-bit physical address (whereas the Unibus only allowed an 18-bit physical address) and block-mode operations for significantly improved bandwidth (which the Unibus did not support).

The CPU's microcode includes a debugger: firmware with a direct serial interface (RS-232 or current loop) to a terminal. This let the operator do debugging by typing and reading octal numbers, rather than operating switches and reading lights, the typical debugging method at the time. The operator could thus examine and modify the computer's registers, memory, and input/output devices, diagnosing and correcting failures in software and peripherals except a failure that disabled the microcode itself. On a failure that kept the LSI-11 from booting, the operator could command it to boot from a different disk.

Both innovations increased the reliability and decreased the cost of the LSI-11.

Later Q-Bus based systems such as the LSI-11/23, /73, and /83 were based upon chip sets designed in house by Digital Equipment Corporation. Later PDP-11 Unibus systems were designed to use similar Q-Bus processor cards, sometimes with a special memory bus for improved speed, using a Unibus adapter to support existing Unibus peripherals.

There were significant other innovations in the Q-Bus lineup. A system variant of the PDP-11/03 introduced full system Power-On Self-Test (POST) and the 11/83 introduced a primitive (by today's standards) anticipatory CPU cache pre-load as well as a high-speed private memory interconnect (bus).

The chip set was not restricted to implementing a PDP-11; a published book^[3] gives the complete source listing of microcode that instead implements the APL programming language.

[edit] The decline of the PDP-11

The basic design of the PDP-11 was sound and was continually updated to use newer technologies. However, in the 1980s, inexpensive VLSI memory chips made large amounts of memory affordable and the PDP-11's 16-bit limit on logical addresses proved insurmountable.

This article describes (here) the hardware and software techniques used to work around this limitation.

DEC's successor to the PDP-11, the VAX (for "Virtual Address Extension") overcame the 16-bit limitation, but was initially a superminicomputer aimed at the high-end time-sharing market. The early VAXes provided a PDP-11 compatibility mode under which much existing software could be immediately used.

Microprocessor chips such as the Motorola 68000 and Intel 80386 began to support 32-bit logical addresses as well. The eventual mass-production of those chips eliminated any cost advantage for the 16-bit PDP-11. A line of personal computers based on the PDP-11, the DEC Professional series, failed commercially, along with other non-PDP-11 PC offerings from DEC.

DEC discontinued PDP-11 production in 1997,^{[citation needed]} and sold the PDP-11 design and system software rights to Mentec, Inc., an Irish producer of LSI-11 based boards for Q-Bus and ISA architecture personal computers. For several years, Mentec produced new PDP-11 processors.

By the late 1990s, not only DEC but most of the New England computer industry which had been built around minicomputers similar to the PDP-11 collapsed in the face of microcomputer-based workstations and servers.

[edit] PDP-11 lore

A (false) folk myth is that the instruction set architecture of the PDP-11 influenced the idiomatic use of the C programming language. The PDP-11's increment and decrement addressing modes correspond to the −−i and i++ constructs in C. If i and j were both register variables, an expression such as *(−−i) = *(j++) could be compiled to a single machine instruction. A further claim is that the lack of different opcodes for single and double floating point operations resulted in the mapping of single precision operations to double precision in the language. Dennis Ritchie unambiguously contradicts this folk myth.^[4]

[edit] Architectural details

The following information is found in DEC's PDP-11 Processor Handbook (see Gordon Bell's 1969 edition).

[edit] Memory management

The PDP-11's 16-bit addresses can address 64K bytes. By the time the PDP-11 yielded to the VAX, 8-bit bytes and hexadecimal notation were becoming standard in the industry; however, numeric values on the PDP-11 always used octal notation, and the amount of memory attached to a PDP-11 was always stated as a number of words. The basic logical address space was 32K words, but the high 4K (addresses 160000 through 177777) was not populated because input/output registers on the bus responded to addresses in that range. So originally, a fully-loaded PDP-11 had 28K words.

The processor reserved low memory addresses for two-word vectors that gave a program counter and processor status word with which to begin a service routine. When an I/O device interrupted a program, it would place the address of its vector on the bus to indicate which service routine should take control. The lowest vectors were service routines to handle various types of trap. Traps occurred on some program errors, such as arithmetic overflow or an attempt to execute an undefined instruction; and also when the program executed an instruction such as BPT, EMT, IOT, or TRAP to request service from the operating system.

[edit] Memory expansion

This article described how the 16-bit logical address space was an insurmountable limitation. During the life of the PDP-11, the following techniques were used to work around the limitation:

• Later-model PDP-11 processors included memory management to support virtual addressing. The physical address space was extended to 18 or 22 bits, though the logical address space remained limited to 16 bits.
• Some models, beginning with the PDP-11/45, could be set to use 32K words (64K bytes) as the "instruction space" for program code and a separate 32K words of "data space." Some operating systems, notably Unix since edition V7, and RSX11-M+, relied on this feature.
• Programming techniques could conceal paging issues from the application programmer. For example, in the Modula-2 language, the compiler produced code under which the run-time system would swap 8-Kb pages into the logical address space as individual procedures received control. (See the external reference here.)

[edit] Data formats

16-bit words were stored little-endian with least significant bytes first. Due to the popularity of the PDP-11, this format is still sometimes referred to as pdp-endian. 32-bit data (supported as extensions to the basic architecture, e.g., floating point in the FPU Instruction Set, double-words in the Extended Instruction Set or long data in the Commercial Instruction Set) were stored in more than one format, including an unusual middle-endian format.^[5][6]

[edit] Addressing modes

Most instructions allocate six bits to specify an operand. Three bits select one of eight addressing modes, and three bits select one of the eight general registers. The use of three-bit groups made octal notation natural.

In the following sections, each item includes an example of how the operand would be written in assembly language for a hypothetical single-operand instruction with symbol OPR. Rn means one of the registers, written R0 through R7. (Rn) signifies the contents of that register.

[edit] General register addressing modes

The following eight modes can be applied to any general register. Their effects when applied to R6 (the stack pointer, SP) and R7 (the program counter, PC) are set out separately in the following sections.

Code	Name	Example	Description
0n	Register	OPR Rn	The operand is in Rn
1n	Register deferred	OPR (Rn)	Rn contains the address of the operand
2n	Autoincrement	OPR (Rn)+	Rn contains the address of the operand, then increment Rn
3n	Autoincrement deferred	OPR @(Rn)+	Rn contains the address of the address, then increment Rn by 2
4n	Autodecrement	OPR -(Rn)	Decrement Rn, then use it as the address
5n	Autodecrement deferred	OPR @-(Rn)	Decrement Rn by 2, then use it as the address of the address
6n	Index	OPR X(Rn)	(Rn)+X is the address of the operand
7n	Index deferred	OPR @X(Rn)	(Rn)+X is the address of the address

In index and index deferred modes, X is a 16-bit value taken from a second word of the instruction. In double-operand instructions, both operands can use these modes. Such instructions are three words long.

Autoincrementation and autodecrementation of a register is by 1 in byte instructions, by 2 in word instructions, and by 2 whenever a deferred mode is used, since the quantity the register addresses is a (word) pointer.

[edit] Program counter addressing modes

When R7 (the program counter) is specified, four of the addressing modes naturally yield useful effects:

Code	Name	Example	Description
27	Immediate	OPR #N	The operand is contained in the instruction
37	Absolute	OPR @#A	The absolute address is contained in the instruction
67	Relative	OPR A	An extra word in the instruction is added to PC+2 to give the address
77	Relative deferred	OPR @A	An extra word in the instruction is added to PC+2 to give the address of the address

The only common use of absolute mode, whose syntax combines immediate and deferred mode, was to specify input/output registers, as the registers for each device had absolute memory addresses. Relative mode has a simpler syntax and was the preferred mode for referring to program variables and jump destinations. A program that used relative mode (and relative deferred mode) exclusively for internal references was position-independent; it contained no assumptions about its own location, so it could be loaded into an arbitrary memory location, or even moved, with no need for the code to be adjusted to reflect its location. In computing such internal references relative to the current location, the processor performed relocation on the fly.

Immediate and absolute modes are merely autoincrement and autoincrement deferred mode, respectively, applied to PC. Whether the auxiliary word is "in the instruction" as the above table says, or is found following an instruction that also increments PC past it, is subjective. As PC always points to words, the autoincrementation is always by 2.

[edit] Stack addressing modes

R6, also written SP, is used as a hardware stack for traps and interrupts. A convention enforced by the set of modes the PDP-11 provided is that a stack grew downward (toward lower addresses) as items were pushed onto it. When a mode is applied to SP, or to any register the programmer elects to use as a software stack, the addressing modes have the following effects:

Code	Name	Example	Description
16	Deferred	(SP)	The operand is on the top of the stack
26	Autoincrement	(SP)+	The operand is on the top of the stack, then pop it off
36	Autoincrement deferred	@(SP)+	A pointer to the operand is on top of the stack; pop the pointer off
46	Autodecrement	-(SP)	Push a value onto the stack
66	Indexed	X(SP)	This refers to any item on the stack by its positive distance from the top
76	Indexed deferred	@X(SP)	This refers to a value to which a pointer is at the specified location on the stack

Although software stacks could contain bytes, SP is always a stack of words. Autoincrementation and autodecrementation of SP is always by 2.

[edit] Instruction set

The PDP-11 operates on bytes and words. Bytes are specified by a register number (identifying the register's low-order byte) or by a memory location. Words are specified by a register number or by the memory location of the low-order byte, which must be an even number. In most instructions that take operands, bit 15 is set to specify byte addressing, or clear to specify word addressing. In the lists in the following two sections, the assembly-language programmer appended B to the instruction symbol to specify a byte operation; for example, MOV became MOVB.

[edit] Double-operand instructions

The high-order 4 bits specify the operation to be performed (with bit 15 generally selecting word versus byte addressing). Two groups of 6 bits specify mode and register, as defined above, for each of two operands.

15			12	11		9	8		6	5		3	2		0
Opcode				Mode			Register			Mode			Register

• MOV (move) first operand to second operand
• ADD operands; sum overwrites second operand
• SUB (subtract); difference overwrites second operand
• BIT (bit test): AND operands and set condition codes; neither operand changes
• BIC (bit clear): clear bits of second operand that are 1s in first operand
• BIS (bit set, or inclusive OR); result overwrites second operand
• XOR (exclusive OR); result overwrites second operand

The ADD and SUB instructions use word addressing, and have no byte-oriented variations.

[edit] Single-operand instructions

The high-order 9 bits specify the operation to be performed (with bit 15 generally selecting word versus byte addressing). (There are not as many operations as it seems, as most combinations of the high-order 4 bits are taken by the double-operand instructions.) A single group of 6 bits specifies mode and register, as defined above, for the single operand.

15									6	5		3	2		0
Opcode										Mode			Register

• CLR (clear)
• COM (ones complement)
• INC (increment)
• DEC (decrement)
• NEG (twos complement negate)
• TST (test)
• ASR (arithmetic shift right)
• ASL (arithmetic shift left)
• ROR (rotate right)
• ROL (rotate left)
• SWAB (swap bytes)
• ADC (add carry)
• SBC (subtract carry)
• SXT (sign extend)

The SWAB instruction, which swaps the high-order and low-order byte of the specified word, does not have two variations for byte- and word-addressing.

[edit] Program Control instructions

The high-order byte specifies the operation. The low-order byte is an offset relative to the current location of the program counter. The offset is a number of words (so it is multiplied by 2 before being combined with the program counter) and it is a signed number, enabling branches forward and backward in the code.

15							8	7							0
Opcode								Offset

• BR (branch unconditionally)
• BNE (branch if not zero)
• BEQ (branch if zero)
• BPL (branch if plus)
• BMI (branch if minus)
• BVC (branch if overflow clear)
• BVS (branch if overflow set)
• BCC (branch if carry clear)
• BCS (branch if carry set)
• BLE (branch if ≤ 0)
• BGE (branch if ≥ 0)
• BLT (branch if < 0)
• BGT (branch if > 0) (signed compares)
• BLO (branch if lower)
• BHI (branch if higher)
• BLOS (branch if lower or same)
• BHIS (branch if higher or same) (unsigned compares).
• SOB (subtract one from register and branch if not = 0).

The limited range of the branch instructions meant that, as code grew, the target addresses of some branches would become unreachable. The programmer would change the one-word BR to the two-word JMP instruction from the next group. As JMP has no conditional forms, the programmer would change BEQ to a BNE that branched around a JMP.

[edit] Jump & Subroutine instructions

• JMP (jump)
• JSR (jump to subroutine--see below)
• RTS (return from subroutine--see below)
• MARK (support of stack clean-up at return)
• EMT (emulator trap)
• TRAP, BPT (breakpoint trap)
• IOT (input/output trap)
• RTI & RTT (return from interrupt).

The JSR instruction could save any register on the stack. Programs that did not need this feature specified PC as the register (JSR PC,address) and the routine returned using RTS PC. If a routine were called with, for instance, "JSR R4, address", then the old value of R4 would be on the top of the stack and the return address (just after JSR) would be in R4. This let the routine gain access to values coded in-line by specifying (R4)+, or to in-line pointers by specifying @(R4)+. The autoincrementation moved past these data, to the point at which the caller's code resumed. Such a routine would have to specify RTS R4 to return to its caller.

[edit] Miscellaneous instructions

• HALT, WAIT (wait for interrupt)
• RESET (reset UNIBUS)
• MTPD (move to previous data space)
• MTPI (move to previous instruction space)
• MFPD (move from previous data space)
• MFPI (move from previous instruction space)
• MTPS (move to processor status word)
• MFPS (move byte from processor status word).

[edit] Condition Code operations

• CLC, CLV, CLZ, CLN, CCC (clear relevant condition code)
• SEC, SEV, SEZ, SEN, SCC (set relevant condition code).

The four condition codes in the processor status word (PSW) are

• N indicating a negative value
• Z indicating a zero (equal) condition
• V indicating an overflow condition, and
• C indicating a carry condition.

SCC and CCC respectively set and clear all four condition codes.

[edit] "Extended Instruction Set" (EIS)

The EIS was an option for 11/35/40 and 11/03, and was standard on newer processors.

• MUL, DIV multiply and divide integer operand to register pair
• ASH, ASHC arithmetic - shift a register or a register pair. For a positive number it will shift left, and right for a negative one.

[edit] "Floating Instruction Set" (FIS)

The FIS instruction set was an option for the PDP-11/35/40 and 11/03

• FADD, FSUB, FMUL, FDIV only for single-precision operating on stack addressed by register operand

[edit] "Floating Point Processor" (FPP)

This was the optional floating point processor option for 11/45 and most subsequent models.

• full floating point operations on single- or double-precision operands, selected by single/double bit in Floating Point Status Register
• single-precision floating point data format predecessor of IEEE 754 format: sign bit, 8-bit exponent, 23-bit mantissa with hidden bit 24

[edit] "Commercial Instruction Set" (CIS)

The CIS microcode option for 11/23/24, add-in modules for the 11/44, and one version of the 11/74.

• Various string and decimal instructions used to support COBOL and Dibol.

[edit] Inconsistent instructions

Over the life of the PDP-11, subtle differences arose in the implementation of instructions and combinations of addressing modes. At one point, about a dozen were documented^{[citation needed]}, though no method was regarded as correct. The inconsistencies did not affect ordinary use of the PDP-11.

For example, the instruction MOV R5,-(R5) moves the value in a register to the address it points to, after decrementing it by two. A microprogrammed PDP-11 might completely evaluate the source operand before starting to evaluate the destination operand, so the value moved would not reflect the decrementation. A PDP-11 implemented by circuitry might perform the decrementation first, because doing so in general might save a memory cycle.

[edit] Interrupts

The PDP-11 operated at a priority level from 0 through 7, declared by three bits in the program status word (PSW).

To request an interrupt, a bus device would assert one of four common bus lines, BR4 through BR7, until the processor responded. Higher numbers indicated greater urgency, perhaps that data might be lost or a desired sector might rotate out of contact with the read/write heads unless the processor responded quickly. The printer's readiness for another character was the lowest priority (BR4), as it would remain ready indefinitely. If the processor were operating at level 5, then BR6 and BR7 would be in order. If the processor were operating at 3 or lower, it would grant any interrupt; if at 7, it would grant none. Bus requests that were not granted were not lost but merely deferred. The device needing service would continue to assert its bus request.

Whenever an interrupt exceeded the processor's priority level, the processor asserted the corresponding bus grant, BG4 through BG7. The bus-grant lines were not common lines but were a daisy chain: The input of each gate was the output of the previous gate in the chain. A gate was on each bus device, and a device physically closer to the processor was earlier in the daisy chain. If the device had made a request, then on sensing its bus-grant input, it could conclude it was in control of the bus, and did not pass the grant signal to the next device on the bus. If the device had not made a request, it propagated its bus-grant input to its bus-grant output, giving the next closest device the chance to reply. (If devices did not occupy adjacent slots to the processor board, "grant continuity cards" inserted into the empty slots propagated the bus-grant line.)

Once in control of the bus, the device dropped its bus request and placed on the bus the memory address of its 2-word vector. The processor saved the program counter (PC) and PSW, and loaded new values from the specified vector. For a device at BR6, the new PSW in its vector would typically specify 6 as the new processor priority, so the processor would honor more urgent requests (BR7) during the service routine, but defer requests of the same or lower priority. With the new PC, the processor jumped to the service routine for the interrupting device. That routine operated the device, at least removing the condition that caused the interrupt. The routine ended with the RTI (ReTurn from Interrupt) instruction, which restored PC and PSW as of just before the processor granted the interrupt.

If a bus request were made in error and no device responded to the bus grant, the processor timed out and performed a trap that would suggest bad hardware.

[edit] MACRO-11 assembly language

MACRO-11 is the assembly language for the PDP-11. It is the successor to PAL-11 (Program Assembler Loader), an earlier version of the PDP-11 assembly language without macro facilities. MACRO-11 was supported on all DEC PDP-11 operating systems. PDP-11 Unix systems also include an assembler (called "as"), structurally similar to MACRO-11 but with different syntax and fewer features.

[edit] PDP-11 models

The PDP-11 processors tended to fall into several natural groups depending on the original design upon which they are based and which I/O bus they used. Within each group, most models were offered in two versions, one intended for OEMs and one intended for end-users.

[edit] Unibus models

The following models used the Unibus as their principal bus:

• PDP-11 (later renamed the PDP-11/20) and PDP-11/15 — The original, non-microprogrammed processor; designed by Jim O'Loughlin.
• PDP-11/35 and 11/40 — A microprogrammed successor to the /20; the design team was led by Jim O'Loughlin.
• PDP-11/45, 11/50, and 11/55 — A much faster microprogrammed processor that could use semiconductor memory instead of or in addition to core memory.
• PDP-11/70 — The 11/45 architecture expanded to allow 4 MB of physical memory segregated onto a private memory bus, 2 KB of cache memory, and much faster I/O devices connected via the Massbus.^[7]
• PDP-11/05 and 11/10 — A cost-reduced successor to the 11/20.
• PDP-11/34 and 11/04 — Cost-reduced follow-on products to the 11/35 and 11/05. The PDP-11/09 and 11/39 model names were documented internally to DEC but never produced for sale. The PDP-11/34 concept was created by Bob Armstrong.

• PDP-11/44 — An extension of the 11/34 that included the cache memory and floating point units as a standard feature. This machine also included a sophisticated serial console and support for 4 MB of physical memory. The design team was managed by John Sofio. NOTE: DEC documentation (PDP-11/44 System User's Guide, EK-11044-UG-003) shows the floating point unit as an option (FPP-11F). Moreover, others have documented the 11/44 as a descendent of the 11/45 and 11/70; the 11/34 was of a different 'lineage', following the 11/05.
• PDP-11/60 — A PDP-11 with user-writable microcontrol store; this was designed by another team led by Jim O'Loughlin.
• PDP-11/24 — First VLSI PDP-11 for Unibus, using the "Fonz-11" (F11) chip set
• PDP-11/84 — Using the VLSI "Jaws-11" (J11) chip set
• PDP-11/94 — J11-based, faster than 11/84

[edit] Q-bus models

The following models used the Q-Bus as their principal bus:

• PDP-11/03 (also known as the LSI-11/03) — The first LSI PDP-11, this system used a chipset from Western Digital.

• PDP-11/23 — 2nd generation of LSI (F-11), early units only supported 248 KB memory, but could be modified for 4 MB support
• PDP-11/23+/MicroPDP-11/23 — Improved 11/23 with more functions on processor card (physically a quad-size card rather than dual)

• MicroPDP-11/73 — The third generation LSI PDP, this system used the "Jaws-11" (J-11) chip set.

• MicroPDP-11/53 — slower 11/73 with on-board memory

• MicroPDP-11/83 — faster 11/73 with PMI (private memory interconnect)

• MicroPDP-11/93 — faster 11/83; final DEC Q-Bus PDP-11 model.

• Mentec M100 — Mentec redesign of the 11/93, with J-11 chipset at 19.66 MHz, 4 onboard serial ports, 1-4 MB on-board memory, and optional FPU.

• Mentec M11 — processor upgrade board; last microcode implementation of PDP-11 instruction set by Mentec, using the TI 8832 ALU and TI 8818 microsequencer from Texas Instruments

• Quickware QED-993 — high performance PDP-11/93 processor upgrade board

[edit] Models without standard bus

• PDT-11/110
• PDT-11/130
• PDT-11/150

The PDT series were desktop systems marketed as "smart terminals". The /110 and /130 were housed in a VT100 terminal enclosure. The /150 was housed in a table-top unit which included two 8" floppy drives, 3 asynchronous serial ports, 1 printer port, 1 modem port and 1 synchronous serial port and required an external terminal. All three employed the same chipset as used on the LSI-11/03 and LSI-11/2 in four "microm"s. There was an option which combined two of the microms into one dual carrier, freeing one socket for an EIS/FIS chip.

• PRO-325
• PRO-350
• PRO-380

The DEC Professional series were desktop PCs intended to compete with IBM's earlier 8088 and 80286 based personal computers. The models were equipped with 5 1/4" floppy disk drives and hard disks, except the 325 which had no hard disk. The original operating system was P/OS, which was essentially RSX-11M+ with a menu system on top. As the design was intended to avoid software exchange with existing PDP-11 models, their ill fate in the market was no surprise for anyone except DEC. RT-11 was eventually ported to the PRO series. A port to the PRO for RSTS/E was also done internal to DEC, but was not released. The PRO-325 and -350 units were based on the DCF-11 ("Fonz") chipset, the same as found in the 11/23, 11/23+ and 11/24. The PRO-380 was based on the DCJ-11 ("Jaws") chipset, the same as found in the 11/53,73,83 and others, though running only at 10 MHz because of limitations in the support chipset.

[edit] Models that were planned but never introduced

• PDP-11/27 — A Jaws-11 implementation that would have used the VAXBI Bus as its principal I/O bus.
• PDP-11/68 — A follow-on to the PDP-11/60 that would have supported 4 MB of physical memory.
• PDP-11/74 — A PDP-11/70 that was extended to contain multiprocessing features. Up to four processors could be interconnected, although the physical cable management became unwieldy. Another variation on the 11/74 contained both the multiprocessing features and the Commercial Instruction Set. A substantial number of prototype 11/74's (of various types) were built and at least two multiprocessor systems were sent to customers for beta testing, but no systems were ever officially sold. A four processor system was maintained by the RSX-11 operating system development team for testing and a uniprocessor system served PDP-11 engineering for general purpose timesharing. The 11/74 was due to be introduced around the same time as the announcement of the new 32 bit product line and the first model - the VAX 11/780. Rumour/Legend or conspiracy theory held that the reason the 11/74 was cancelled was due to its higher performance compared to the 11/780 (see, for example [1]). Marketing was therefore concerned that the availability of a higher performing PDP-11 would slow migration to the new VAX. This was not the case. Rather, the ability to maintain the product in the field was the issue. However conspiracy or not, DEC was never able to successfully migrate its entire PDP-11 customer base to the VAX. The primary reason was not performance, but the PDP-11's superior real-time responsiveness.

[edit] Special purpose versions

• GT40 — VT11 vector graphic terminal using a PDP-11/05
• GT42 — VT11 vector graphic terminal using a PDP-11/10
• GT44 — VT11 vector graphic terminal using a PDP-11/40
• GT62 — VS60 vector graphic workstation using a PDP-11/34a
• H-11 — Heathkit OEM version of the LSI-11/03
• VT20 — Terminal with PDP-11/05 with direct mapped character display for text editing and typesetting (predecessor of the VT71)
• VT71 — Terminal with LSI-11/03 and QBUS backplane with direct mapped character display for text editing and typesetting
• VT103 — VT100 with backplane to host an LSI-11
• VT173 — A high-end typseset terminal containing an 11/03
• MINC-11 — Laboratory system based on 11/03 or 11/23; when based on the 11/23, it was sold as a 'MINC-23', but many MINC-11 machines were field-upgraded with the 11/23 processor. Early versions of the MINC-specific software package would not run on the 11/23 processor because of subtle changes in the instruction set; MINC 1.2 is documented as compatible with the later processor.
• C.mmp — Multiprocessor system from Carnegie Mellon University
• SBC 11/21 (boardname KXT11) Falcon and Falcon Plus — single board computer on a Qbus card implementing the basic PDP11 instruction set, based on T11 chipset containing 32KB static RAM, 2 ROM sockets, 3 serial lines, 20 bits parallel I/O, 3 interval timers and a 2-channel DMA controller. Up to 14 Falcons could be placed into one Qbus system.

[edit] Unauthorized clones

The PDP-11 was sufficiently popular that many unauthorized PDP-11-compatible minicomputers and microcomputers were produced in Eastern Bloc countries. At least some of these were pin-compatible with DEC's PDP-11s and could share peripherals and system software. These include:

• SM-4, SM-1420, SM-1600, Elektronika BK series, Elektronika 60, Elektronika 85, DVK and UKNC (in the Soviet Union)
• SM-4, SM-1420, IZOT-1016 and peripherals (in Bulgaria).
• SM-1420 (in East Germany)
• SM-4 (in Hungary)
• Independent and Coral (in Romania)

[edit] Operating systems

Several operating systems were available for the PDP-11

From Digital:

• BATCH-11/DOS-11
• CAPS-11 (Cassette Based Programme development System)^[8]
• GAMMA-11^[8]
• DSM-11
• IAS
• P/OS
• RSTS/E
• RSX-11
• RT-11
• Ultrix-11

From third parties:

• ANDOS
• CSI-DOS
• DEMOS (Soviet Union)
• Duress (University of Illinois at Urbana-Champaign/Datalogics)^[8]
• Fuzzball
• MERT^[8]
• Micropower Pascal^[8]
• MK-DOS
• MONECS
• MTS (Multi-Tasking System written in RTL/2 by SPL)^[8]
• MUMPS
• PC11 (Decus 11-501/Pilkington)^[8]
• Sphere (Infosphere - Portland Oregon 1981-87)^[8]
• Softech Microsystems UCSD System with UCSD Pascal^[8]
• TRAX (Transaction Processing system)^[8]
• TRIPOS
• TSX-Plus
• Unix (many versions, including Version 7 Unix, UNIX System III, and 2BSD)
• Venix (implementation/port of Unix developed by VenturCom)^[8]

[edit] See also

• SIMH (A multiple minicomputer architecture emulator written in portable C.)

[edit] Notes

[edit] References

• pdp11 processor handbook - pdp11/05/10/35/40, Digital Equipment Corporation, 1973 
• pdp11 processor handbook - pdp11/04/34a/44/60/70, Digital Equipment Corporation, 1979 

[edit] Further reading

• Eckhouse, jr., Richard H.; Morris, L. Robert (1979). Microcomputer Systems Organization, Programming and Applications (PDP-11). Englewood Cliffs, New Jersey: Prentice-Hall. ISBN 0-13-583914-9. 
• Michael Singer, PDP-11. Assembler Language Programming and Machine Organization, John Wiley & Sons, NY: 1980.

[edit] External links

• The PDP-11 FAQ
• Preserving the PDP-11 Series of 16-bit minicomputers
• Gordon Bell and Bill Strecker's 1975 paper, What We Learned From the PDP-11
• Further papers and links on Gordon Bell's site.
• The Fuzzball
• On LSI-11, RT-11, Megabytes of Memory and Modula-2/VRS by Günter Dotzel, ModulaWare.com - An article on Modula-2 compiler/linker synergy to overcome the PDP/LSI-11 address space limitations, published in DEC PROFESSIONAL, The Magazine for DEC Users, Professional Press, Spring House, PA. U.S.A., January 1986.

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