Adaptive voltage scaling

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Adaptive voltage scaling (AVS) is a closed-loop dynamic power minimization technique that adjusts the voltage supplied to a computer chip to match the chip's power needs during operation. Many computer chips, especially those in mobile devices or Internet of things devices are constrained by the power available (for example, they are limited to the power stored in a battery) and face varying workloads.[1] In other situations a chip may be constrained by the amount of heat it is allowed to generate. In addition, individual chips can vary in their efficiency due to many factors, including minor differences in manufacturing conditions.[2] AVS allows the voltage supplied to the chip, and therefore its power consumption, to be continuously adjusted to be appropriate to the workload and the parameters of the specific chip. This is accomplished by integrating a device that monitors the performance of the chip (a hardware performance manager) into the chip, which then provides information to a power controller.[3]

AVS is similar in its goal to dynamic voltage scaling (DVS) and dynamic voltage and frequency scaling (DVFS). All three approaches aim to reduce power usage and heat generation.[4] However AVS adapts the voltage directly to the conditions on the chip,[5] allowing it to address real-time power requirements as well as chip-to-chip variations and changes in performance that occur as the chip ages.

Dynamic Approaches to reduce power in digital circuits

Background[edit]

Technological advances have enabled very powerful and versatile computing systems to be implemented on smaller chips. As this allows a larger number of functions to take place in the same area, both current density and the associated power dissipation become more concentrated compared to larger chips. The power consumption and thermal performance of integrated circuits has become a limiting factor for high-performance systems.[6][7][8] Mobile devices are also limited by the total amount of power available.[5] Minimizing power consumption in digital CMOS circuits requires significant design effort at all levels. Supply voltage reduction is one way to achieve this, but static supply voltage reduction can reduce performance. Dynamic voltage scaling systems are used to adjust the supply voltage to the specific operations the chip is performing. However, conventional DVS systems do not directly monitor the performance of the chip and must therefore accommodate operation under worst-case performance scenarios.[5] AVS aims to supply each individual domain of the system on the chip with just enough voltage to perform its task under the conditions actually experienced by the chip, minimizing power consumption per processor domain.[4]

Advantages of AVS[edit]

Adaptive voltage scaling is a closed-loop DVS approach that evaluates different factors, such as process variations from device to device on a chip, temperature fluctuations during chip operations, and load variations, and establishes a voltage-frequency relationship for the circuit under those conditions. Each individual chip's process corner is determined either during manufacturing or during runtime and the optimal voltage-frequency relationship is determined and subsequently used for voltage optimization. The advantages offered by this approach are:[4]

  • Delivery of the desired voltage to every block of the system despite variations in temperature, process corner and frequency;
  • Processor- and architecture-independent implementation of power reduction;
  • Typical savings of about 55% compared to open-loop Dynamic Voltage Scaling approaches[citation needed].

Adaptive voltage scaling is used to address the energy-saving requirements of application-specific integrated circuits, microprocessors and system on a chip circuits. It is also well-suited for high-volume systems such as data centers and wireless base stations, as well as power-constrained applications such as portable devices, USB peripherals, and consumer electronics.[4]

Comparison between DVS and AVS[edit]

The primary difference between DVS and AVS is that the former has an open loop control architecture whereas the latter is closed-loop. That is, in AVS there is direct feedback between the performance of the chip and the voltage provided to it.

DVS[edit]

A generic DVS system has a performance manager, a phase-locked loop and a voltage regulator.[8] The performance manager uses a software interface to predict the performance requirements of the next task. Once the power requirements have been determined, the voltage and frequency are set by the performance manager. The phase-locked loop accomplishes the frequency scaling depending on the target frequency set by the performance manager. Similarly, the voltage regulator is programmed to scale the supply voltage in order to achieve the target voltage for the task. DVS systems use a one-to-one mapping of the voltage to frequency to perform the voltage scaling. Frequency-voltage pairs are determined by characterizing the chip's performance under worst-case conditions and stored in a lookup table. If conditions are more favorable, there may be a significant over-supply of power.

AVS[edit]

In closed-loop systems such as AVS, actual on-chip conditions are measured and used to determine the target voltage and frequency.[4][8] Several different implementations of AVS have been developed.

Critical Path Emulation[edit]

Critical Path Monitoring Technique for Adaptive Voltage Scaling

One way to determine the voltage-frequency relationship of the chip is to use a critical path emulator.[8] The emulator is tuned during the manufacturing process to closely model the behavior of the chip, and adapts to environmental and process variations. Measuring the behavior of the emulator allows the supply voltage to be automatically adjusted such that the minimum voltage is supplied for the target task.[5]

A ring oscillator that operates at the same voltage as that of the rest of the chip can be used as a critical path emulator. The ring oscillator's measured frequency indicates the voltage-frequency relationship for the chip under the conditions in which it is operating.

Another type of emulator is a "delay chain" of inverters, NAND gates, wire segments, etc. The exact setting of the delay chain is determined during manufacturing after testing. The delay chain is then used to measure the time taken for a process to traverse the chain, simulating the performance of the chip.[8][9][10]

Both the ring oscillator and critical path methods suffer from the problem that they may not offer a perfect simulation of the operation of the chip, so that a safety margin must be included.[9]

Direct measurement of circuit behavior[edit]

An alternative to simulating the behavior of the critical path is to measure circuit performance directly. One implementation of this approach, called Razor, is based on the idea that only a subset of input patterns will activate the longest timing path on the chip. If the voltage is too low, these input patterns will create a timing error. However, chips have error-correction systems built into them, so a low number of errors can be tolerated. The number of errors is measured and used as feedback to the power system: if the number of errors is very low, then the voltage can be dropped to save power; if the number of errors is above a certain threshold, then the voltage must be increased.[5][8][11]

Compensation for age-related performance degradation[edit]

Over time, chips develop negative-bias temperature instability, which increases the voltage required to operate correctly. AVS can be used to mitigate this issue by increasing the voltage to match the new requirements of the system. This is possible only if the operational degradation due to temperature instability is accurately captured by the performance sensor in the AVS system.[10]

See also[edit]

References[edit]

  1. ^ Keller, Ben; Cochet, Martin; Zimmer, Brian; Lee, Yunsup; Blagojevic, Milovan; Kwak, Jaehwa; Puggelli, Alberto; Bailey, Stevo; Chiu, Pi-Feng; Dabbelt, Palmer; Schmidt, Colin; Alon, Elad; Asanovic, Krste; Nikolic, Borivoje (2016). "Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC" (PDF). ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference. pp. 269–272. doi:10.1109/ESSCIRC.2016.7598294. ISBN 978-1-5090-2972-3. S2CID 28473665.
  2. ^ Horowitz, M.; Alon, E.; Patil, D.; Naffziger, S.; Kumar, R.; Bernstein, K. (2005). "Scaling, power, and the future of CMOS" (PDF). IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest. pp. 9–15. doi:10.1109/IEDM.2005.1609253. ISBN 0-7803-9268-X. S2CID 114793159.
  3. ^ Kushwaha, Sunita; Kumar, Sanjay (2016). "Energy Saving Approaches for Scheduling on Parallel Systems - A Review". International Journal of Computer Applications. 152 (4): 38–42. doi:10.5120/ijca2016911798. S2CID 29261059.
  4. ^ a b c d e Texas Instruments — Application Report (March 2014). "Adaptive (Dynamic) Voltage (Frequency) Scaling—Motivation and Implementation". doi:10.1109/TVLSI.2007.896909. S2CID 12638702. {{cite journal}}: Cite journal requires |journal= (help)
  5. ^ a b c d e Gupte, Ajit; Dwivedi, Satyam; Mehta, Nandish; Amrutur, Bharadwaj (2011). "Adaptative Techniques to Reduce Power in Digital Circuits". Journal of Low Power Electronics and Applications. 1 (2): 261–276. doi:10.3390/jlpea1020261.
  6. ^ Nakai, M.; Akui, S.; Seno, K.; Meguro, T.; Seki, T.; Kondo, T.; Hashiguchi, A.; Kawahara, H.; Kumano, K. (2005). "Dynamic voltage and frequency management for a low-power embedded microprocessor". IEEE Journal of Solid-State Circuits. 40 (1): 28–35. Bibcode:2005IJSSC..40...28N. doi:10.1109/JSSC.2004.838021. ISSN 0018-9200. S2CID 62637419.
  7. ^ Rabaey, Jan M. (2009). Low power design essentials. New York: Springer. ISBN 9780387717135. OCLC 405547044.
  8. ^ a b c d e f Elgebaly, M.; Sachdev, M. (2007). "Variation-Aware Adaptive Voltage Scaling System". IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 15 (5): 560–571. doi:10.1109/TVLSI.2007.896909. ISSN 1063-8210. S2CID 12638702.
  9. ^ a b Gupte, Ajit; Dwivedi, Satyam; Mehta, Nandish; Amrutur, Bharadwaj (2011). "Adaptative Techniques to Reduce Power in Digital Circuits". Journal of Low Power Electronics and Applications. 1 (2): 261–276. doi:10.3390/jlpea1020261.
  10. ^ a b Chan, Tuck-Boon; Chan, Wei-Ting Jonas; Kahng, Andrew B. (March 2013). "Impact of Adaptive Voltage Scaling on Aging-Aware Signoff" (PDF). Proceedings of the Conference on Design, Automation and Test in Europe: 1683–1688. CiteSeerX 10.1.1.310.2413. doi:10.7873/DATE.2013.340. ISBN 9781467350716. S2CID 140692.
  11. ^ Calimera, Andrea; Rizzo, Roberto Giorgio (2019). "Implementing Adaptive Voltage Over-Scaling: Algorithmic Noise Tolerance vs. Approximate Error Detection". Journal of Low Power Electronics and Applications. 9 (2): 17. doi:10.3390/jlpea9020017.
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