Talk:Ferranti Argus

Did you Know

Think you meant 8 November 2007. Doesn't appear on the main page today but is shown in the archive.Dsergeant 08:06, 9 November 2007 (UTC)

DMA: All Ferrranti process control computers in the Argus 100, 200, etc. range employed direct memory access, which they termed direct store acess. They also used interrupts. When I have trraced the Argus 350 I shall edit the Argus page for this point. PeterWol 12:57, 1 December 2007 (UTC)

Excellent, thanks! Maury (talk) 12:59, 13 February 2008 (UTC)

Improvements needed to this article

Style

I'm afraid this article still reads like a technical service manual: we don't need the time the machine took to compute an addition, the voltages it used, or even the differences between the models. What would be useful would be a better historical description, to justify this article meeting Wikipedia:Notability, and some serious editing for style (see Wikipedia:Manual of Style). Michaelbusch (talk) 17:27, 27 February 2008 (UTC)

I realize this is an old comment by a retired Wikipedian, but I respectfully disagree. The Argus technical specs are very much of interest in context, and I really can't imagine why they might not be. There's certainly no level of detail here that can't be found in any other computer article, say the Atari 8-bit family or Mac Pro. As to notability, this is well established in the list of references, and I am equally baffled about the basis for this comment. There are no specifics in terms of style (other than those mentioned above), and having been involved in writing the MoS at times, I'm fairly sure we've done a fair job following them.

Or maybe I'm completely full of crap. So I'll ask, does anyone else have problems with the overall "style" of this article? Maury Markowitz (talk) 11:30, 19 October 2012 (UTC)

Comments from 2008 (and certainly earlier) often seem bizarre in what they regard as either important or notable. I'd like to see this article expand, but there's nothing in here that I'd remove. Andy Dingley (talk) 11:38, 19 October 2012 (UTC)

Factually Incorrect and Incomplete

Jtevans48 (talk) 13:38, 8 February 2012 (UTC)

Beginning with the paragraph ASCII Based Designs, the information is not correct and is incomplete. The term ASCII is not correct in this context [American Standard Code for Information Interchange]. I suspect the author means ASIC.

The Argus 600 8-bit computer was never an ASIC design. It was either DTL or TTL SSI, I don't remember which. Once the 700 range became available the 600 was not developed further.

The Argus 700 16 bit computers were not an "ASIC design" until 1979.

From 1973 to 1979 there were several models of Argus 700 based on different technologies:

• Argus 700S - Motorola MECL II or MECL III (MECL 10000) Small Scale Integrated Circuits (SSI)
• Argus 700T1 - single board computer, TTL, SSI
• Argus 700T2 - two board computer, TTL, SSI
• Argus 700E - two board computer, TTL, SSI
• Argus 700G - two coupled boards, Schottky TTL and 4-Bit-slice ALUs (AMD2901) - could be a plug replacement for 700E but had more facility in a new backplane.
• Argus 700F - Ferranti Semiconductor Uncommited Logic Array (ULA) and 4-Bit-slice ALUs.

The Argus 700S was not physically compatible with the TTL range. It had its own 'S' range of memory and perhipheral multiplexor (MX) / communications processor (CMX). The 700S could control and utilise the TTL range of memory and peripherals using an adaptor card and backplane.

[by AJP]

I worked for Ferranti for a long time as a systems programmer through to designer, so I can add some technical details which might help. All this as I remember and to best of my recollection

The 700S was incompatible with other processor cards, because it was ECL based instead of TTL, and so it had its own 'close' modules - memory, communications multiplexor (CMX) , but then it used the same generic peripheral racks/boxes as the rest of the range. The 700S had a design with special 'port connector' ribbon cables for high speed. It originally had its own display panel too, but I seem to remember when seeing an 'S' refurbished, it had the later style black 'G' style control panel.... not sure how that was achieved.

The 700S had the ability to address 256k memory (18 bit) by the use of a 'base+displacement' addressing with a 'virtual address module', where the base would be multiplied by 4 as part of instruction.

The T,E,S were concurrent, and of the same design era (red panels) , whereas the F,G,H were the later design (grey panels with black consoles). I'm not sure if the 700H was ever made, as instead there was a 'GX' and a 'GZ' version with faster processing speeds, and even a 'GZ+' prototype.

The 700G could technically access 2Mb (?) as it had a 24 bit address bus, again done by base+displacement and an extension module, but base was multiplied by 8 as part of instruction. I think it was backwards compatible with 'S' mode as well for 18 bit addressing.

There was also a CMM, which was the F and G type Communications Multiplexor, and a high speed computer to computer interface using a separate channel (called a 'PIC'). These modules could access memory directly and interrupt the CPU, so were semi-autonomous modules.

The hardware had a set of card boxes/racks, where I reckon in modern terms, one rack was a 'CPU bus' which had CPU, memory and any CMM or PIC, and a 'peripheral or I/O bus' rack, which had cards for tape reader, teletype etc. The 'S' had a double (triple?) height rack for its CPU and memory cards, and CMX if present.

The M700 claimed to use the same instruction set, but by the time it went into production it was quite a different beast to the F,G systems, and had unique opcodes and hardware.

Software wise, the operating systems were called OSC20 through to OSC50 on early series. If it had a 5 suffix (e,g, OSC45) then op sys supported the extended addressing via the virtual address module. OSC20 and 25 were all memory based (no disc resident tasks, all built into one bootable image) through to OSC55 which had full handling of named tasks (disc files) with dynamic allocation and task roll-out to disc abilities.

The GX and GZ systems had OSC145 which supported the 24 bit wide addressing. this was later rewritten as OSC245, which also supported shared libraries and had a lower operating system overhead.

The computing language was the Ferranti variant of CORAL 66, and it had extra keywords for stuff like the virtual addressing, and even had built in pointers (like the int* in 'C') by the use of the 'REFERENCE' keyword as a prefix. I remember we made some very efficient data packing by the use of 'REF' 'TAB' structures which could be assigned arbitrarily into array buffers for disc read and write. Very neat, but a little dangerous (very like 'C' !!)

[end -ajp]

ASIC Design - Argus 700F, M700

Work began on the Argus 700F in 1978. A compatible replacement for the Argus 700T2 and 700E, this was based on a number (five?) Ferranti Semiconductor Uncommitted Logic Array (ULA) Mask Programmable chips and 4-bit bit slice ALUs. Before committing to ULA production, the gate array logic was first implemented in a wire wrapped prototype of Schottky TTL SSI, to verify the design.

I believe it was the Argus 700F that was 'militarised' as the M700. Prior to the M700, military projects used the FM1600 from Ferranti, Bracknell.

Differences in models

These TTL / STTL designs used fusible PROMs to implement the Argus 700 instruction set as microcode specific to the model in question. Not all instructions were implemented in all models.

The hardware differences in TTL models were related to the available operating modes (Privileged / Task1 / Task2), maximum addressable memory, the microcode cycle time, main memory access time and cycle time, hardware floating point support, the use of hardware assisted paged virtual memory and an instruction cache. More capable units attracted a higher selling price.

Actually ASCII is the term I was trying to use. ASCII is a 7+1 bit character encoding, vs. earlier schemes that were generally 6 or 6+1 bits. Computers were often designed to efficiently fit multiple characters in a word, so in the 1950s and 60s when 6-bit chars were common, most computers had word lengths of 12, 24 or 36 bits - or in this case, 2 x (6+1) = 14. After the adoption of ASCII, computers generally had word lengths of 8, 16 or 32 bits. This effected the Argus line in the switch of word lengths from 14 to 8 and 16. Similar changes occurred across the entire computer world, following the lead set by the IBM360 - see, for instance, the DEC and CDC lines. So yes, an "ASCII Based Design" is very much what I was going for :-) Maury Markowitz (talk) 11:35, 19 October 2012 (UTC)

Early computers (including those of this relatively late vintage) had little interest in text processing. Text was processed on typewriters, by secretaries, and it wasn't until the end of the '70s that this was cost-effectively bettered. Early computers were for algorithmic numerical computations. Mechanical adding machines were a cheaper capital cost for simple arithmetic, so unless the work needed volume, complexity, precision or speed, then it was still difficult to justify computerisation. Storage was limited in size, so database work was still the province of IBM's electromechanical tabulators. Apart from LEO in the UK, and IBM's eye to the future markets, computers were big expensive things that worried about high precision floating point calculations above all else. Look at the programming languages of the day: Fortran had powerful maths support from the outset, but took decades before its string capacity outperformed even MS-BASIC. The Argus is pretty much the same age as COBOL, yet I don't think Ferranti ever offered it for it.

So character operations were supported and were even important, but architectural factors, most importantly word length, were based on the precision needed for the floating point libraries. This word length was then subdivided into some usable character size chunks (6 bits being popular), according to how it could be subdivided in a usefully workable fashion, whether this matched up with ASCII or not.

I don't know when the first 8 bit machine (or 16 bit machine) was developed (probably a New England mini) where this was done with a deliberate eye to character processing, rather than floating point, but it's an interesting question. Andy Dingley (talk) 17:14, 20 October 2012 (UTC)

A note on ASICs - these obviously play no part in a 1950s machine built out of geraniums. However Ferranti were the first big UK player in ULAs from the late 1970s (and the broad topic of ASICs, even though the technique of making them is significantly different), so I wouldn't rule out some early Ferranti ULA research being focussed on using ULAs within their computing lines, very possibly by emulating the later Argus architectures.

ULAs (programmed by late-fabrication-stage metallisation wiring or fuse blowing) eventually became a bit of a dead-end in favour of ASICs designed from silicon design libraries. However that route to ASICs couldn't happen until the availability of cheap in-house computing of the PDP 11 scale, which itself post-dates the Argus. Andy Dingley (talk) 17:24, 20 October 2012 (UTC)

Well I do know that the IBM 360 was a 32-bit machine specifically to fit ASCII chars, which were in the process of final definition at just that time. IBM had previously used a 6-bit code and all of their machines from that era used words with base-6. However, IBM was a strong proponent of ASCII, and deliberately designed the 360 to allow switching between 8-bit ASCII and an extended char code of their own, EBCDIC, which was designed to store the 6-bit codes in 8-bits to allow simplified backward compatibility with older peripherals. See note 3 in the 360 article for some more background. My feeling: I'm not sure the separation between char form and word length is nearly as firm as you imply above. Maury Markowitz (talk) 18:08, 29 November 2012 (UTC)

Oh, and I shouldn't forget the move away from BCD either. Maury Markowitz (talk) 18:10, 29 November 2012 (UTC)

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"Hearing aid computer"

This section claims that the Mullard OC71 transistors used in this design were developed for use in hearing aids. There is no ref for this (or indeed the 'hearing aid computer' name). The OC7x series was a general purpose alloy junction audio transistor hand selected into three types - OC70 (low noise), OC71 (general purpose), and OC72 (high current). A bit later Mullard/Philips refined the process to improve HF performance yielding the OC44 (HF), OC45 (IF) and OC46 (switching).

While OC71s were certainly used in some late 50s hearing aids, they weren't specifically developed for that purpose. That's not to say that there wasn't a widely held belief within Ferranti that they were, though. --Ef80 (talk) 17:06, 2 February 2021 (UTC)

@Ef80: The term appears in the original Aylen document, which states "using low power hearing aid transistors" right in the abstract along with many additional mentions within. The most detailed is "Maurice Gribble developed a prototype digital controller around 1956 using low-frequency junction transistors meant for hearing aid use (25 kHz) made by Mullard known as OC71.37". That seems pretty direct to me. As you say, this might simply be Ferranti's belief, but for now I think we have enough to leave the claim in the article. Maury Markowitz (talk) 18:35, 1 August 2023 (UTC)

OK. It's certainly not a sufficiently important point to lose sleep over. There may have been an OC71 subtype with characteristics originally suited to hearing aid use - low voltage requirements maybe, or low leakage. Transistors of that era had a wide spread of characteristics and were individually hand selected for particular applications. Ef80 (talk) 09:13, 2 August 2023 (UTC)