Talk:IBM System/360 Model 85

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Organization[edit]

I have two issues with the way the article is currently organized:

IBM System/360 Model 85#Advanced/special features begins with 'The system console is L-shaped: ...', which is certainly worth mentioning but is neither advanced nor special. I'm not sure whether to change the heading or to create a separate section.
The reference to the 360/25 has a redundant mention of the 85 announcement date but no mention of the 25 announcement date. Would 'The Model 85 has both Read-only and Writeable Control Storage[4]:p.14 (it is the second System/360 to have writeable control storage; the IBM System/360 Model 25, announced earlier in the same month as the 360/85, is the first to have writeable control storage.' be better? Shmuel (Seymour J.) Metz Username:Chatul (talk) 15:55, 14 March 2019 (UTC)[reply]

IBM's first commercially available computer with cache memory[edit]

As far as I know, it is the first commercially available by anyone. Is it not? Gah4 (talk) 01:54, 17 June 2020 (UTC)[reply]

According to CPU cache#First data cache, it is; unless somebody can find a reliable source for an earlier commercially-available cache, we might as well just say "the first commercially available computer with cache memory". (If somebody does find one, this page and CPU cache will need to be updated.)

(And, yes, CPU cache should perhaps say "instruction and data cache" or something such as that, unless instruction fetch didn't go through the "buffer", to clarify that there wasn't a split cache.) Guy Harris (talk) 04:34, 17 June 2020 (UTC)[reply]

There is a whole IBM Systems Journal article about the cache, but it was a while ago when I read it. I believe that split cache came later, but it is a good question. They did a lot of studies, including using tapes of instruction traces from real programs. Gah4 (talk) 08:12, 17 June 2020 (UTC)[reply]

"Structural aspects of the System/360 Model 85, II - The cache" (Volume 7, Number 1, 1968, so they were calling it a "cache" by that point). They don't explicitly say whether both instruction and data fetches go through the cash, so my guess is that they do.

Note that a processor can have an instruction-only or data-only cache rather than a split cache; the Motorola 68020 had a 256-byte on-chip instruction cache and no on-chip data cache, for example. Guy Harris (talk) 09:26, 17 June 2020 (UTC)[reply]

There's another complication; the 2085 had an I-unit that ran in parallel to the E-unit and pre-fetched instructions. Would you consider it, and similar instruction pipelines on older machines, to be a form of L1 instruction cache? Shmuel (Seymour J.) Metz Username:Chatul (talk) 10:12, 17 June 2020 (UTC)[reply]

Not unless they stored some fetched instructions in memory faster than main memory and, if they were to be executed again, used their stored copies - i.e.. if they include an instruction cache. Guy Harris (talk) 10:16, 17 June 2020 (UTC)[reply]

Some machines^[1] had fast branches within the pipeline. If the branch was too far away from its target then it had to refill the pipeline. The question is whether the term cache; encompasses such a specialized case. Shmuel (Seymour J.) Metz Username:Chatul (talk) 16:45, 17 June 2020 (UTC)[reply]

I'd consider that sufficiently specialized as to consider the M85's cache as the first implementation of what we generally think of as a cache. The Motorola 68010 had something similar - if a loop consisted of a processing instruction and a branch, that would run without making main memory references for instructions once the two instructions have been fetched for the first time. The page for the 68010 says it "acts like a tiny special-case instruction cache", but I'd consider that sufficiently special-case as to be different from what the M85 had - and what the Motorola 68020 had (a general-purpose 256-byte Icache) and what the Motorola 68030 had (separate 256-nbyte Icache and Dcache). Guy Harris (talk) 18:53, 17 June 2020 (UTC)[reply]

S/360 allows for self-modifying code. There is special logic for the 360/91 to detect modifying after prefetch. The 360/91 doesn't have data cache, but special loop mode that keeps some previously fetched instructions for small loops. No fancy association like cache usually has, just sequential locations. Well, the 360/91 can also prefetch on two branch paths... Gah4 (talk) 19:51, 17 June 2020 (UTC)[reply]

References

^ Roland N Ibbett; Nigel P Topham (1996), "Instruction buffering in the CDC 6600", HIGH PERFORMANCE COMPUTER ARCHITECTURES - A Historical Perspective, and when executing loops which can be contained within the stack, no Central Storage accesses for instructions are required at all. {{citation}}: External link in |sectionurl= (help); Unknown parameter |sectionurl= ignored (|section-url= suggested) (help)

[1] Roland N Ibbett; Nigel P Topham (1996), "Instruction buffering in the CDC 6600", HIGH PERFORMANCE COMPUTER ARCHITECTURES - A Historical Perspective, and when executing loops which can be contained within the stack, no Central Storage accesses for instructions are required at all. {{citation}}: External link in |sectionurl= (help); Unknown parameter |sectionurl= ignored (|section-url= suggested) (help)

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