Template:AMD Turion II (Caspian, dual-core)

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Model number Clock
speed
L2 cache FPU width[1] Hyper
Transport
Multi TDP Socket Release date Part number
Turion II M500 2.2 GHz 2 × 512 KB 128-bit 1.8 GHz 11× 35 W Socket S1G3 September 10, 2009 TMM500DBO22GQ
Turion II M520 2.3 GHz 2 × 512 KB 128-bit 1.8 GHz 11.5× 35 W Socket S1G3 September 10, 2009 TMM520DBO22GQ
Turion II M540 2.4 GHz 2 × 512 KB 128-bit 1.8 GHz 12× 35 W Socket S1G3 September 10, 2009 TMM540DBO22GQ
Turion II M560 2.5 GHz 2 × 512 KB 128-bit 1.8 GHz 12× 35 W Socket S1G3 April 2010 TMM560DBO22GQ

References

  1. ^ "The 2009 AMD Mainstream Platform". Amd.com. Retrieved 2014-04-30.