Draft:1 nm process

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Declined by SafariScribe 11 days ago. Last edited by Auric 11 days ago. Reviewer: Inform author.

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In semiconductor manufacturing, the "1 nm process" is the next MOSFET (metal–oxide–semiconductor field-effect transistor) die shrink after the "2 nm" process node.

The term "1 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by the Institute of Electrical and Electronics Engineers (IEEE), a "1 nm node range label" is expected to have a contacted gate pitch of 42 nanometers and a tightest metal pitch of 16 nanometers. The first 1 nm chips are expected to be launched in 2027^[1]

References

^ "IRDS™ 2021: More Moore - IEEE IRDS™". Archived from the original on 2022-08-07.

[1] "IRDS™ 2021: More Moore - IEEE IRDS™". Archived from the original on 2022-08-07.

[1]