Draft:Lunar Lake
| General information | |
|---|---|
| Launched | 2025 |
| Marketed by | Intel |
| Designed by | Intel |
| Common manufacturers | |
| Cache | |
| L1 cache | 112 KB per P-core (64 KB instructions + 48 KB data) 96 KB per E-core and LP E-core (64 KB instructions + 32 KB data) |
| L2 cache | 2 MB per P-core 4 MB per E-core cluster |
| Architecture and classification | |
| Application | Low-power mobile |
| Technology node | TSMC N3B |
| Microarchitecture | Lion Cove (P-cores) Skymont (E-cores) |
| Instructions | x86-64 |
| Physical specifications | |
| Cores |
|
| Products, models, variants | |
| Product code name |
|
| Variant | |
| History | |
| Predecessor | Meteor Lake |
| Successor | Nova Lake (Draft) |
Lunar Lake is the code name of an upcoming low power microprocessor using Intel 18A process and TSMC nodes. Lunar Lake is set to ship in 2025.[1][2][3]
Features[edit]
Lunar Lake has 3 tiles, Compute+Graphics, SoC and I/O.
CPU[edit]
Further information:
- 4 Lion Cove performance CPU cores (P-core)
- 4 Skymont efficient CPU cores (E-core)
GPU[edit]
- Intel Arc Battlemage (Gen13) tile GPU
- Up to 8 Xe2-cores, 128 Xe2 Vector Engines(XVE)
- H.266/VVC fixed-function hardware decoding
NPU[edit]
- Integrated Intel AI Boost NPU 4.0 AI accelerator
- 48 TOPS[4]
- 4x Meteor Lake's NPU performance
I/O[edit]
- On-package LPDDR5x-8533 memory
List of Core Ultra Series 2 CPUs[edit]
Lunar Lake-V[edit]
References[edit]
- ^ https://www.intel.com/content/www/us/en/newsroom/news/intel-technology-roadmaps-milestones.html
- ^ https://download.intel.com/newsroom/2022/corporate/2022-Intel-Investor-Meeting-Client.pdf
- ^ https://www.extremetech.com/computing/intel-ceo-confirms-arrow-lake-will-feature-tsmc-3nm-gpu-tiles
- ^ https://videocardz.com/press-release/intel-unveils-lunar-lake-with-lioncove-skymont-cpu-cores-and-xe2-gpu