Nader Bagherzadeh
Nader Bagherzadeh | |
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| Born | Nader Bagherzadeh نادر باقرزاده April 13, 1955; Tehran, Iran |
| Nationality | American |
| Alma mater | The University of Texas at Austin |
| Awards | IEEE Fellow (2014) |
| Scientific career | |
| Fields | Computer Architecture, Network-on-Chip, System-on-Chip, Machine Learning, 3D IC, Reconfigurable Computing |
| Institutions | University of California, Irvine |
| Website | engineering |
Nader Bagherzadeh (Persian: نادر باقرزاده) is a professor of computer engineering in the Department of Electrical Engineering and Computer Science at the University of California, Irvine, where he served as a chair from 1998 to 2003. Bagherzadeh has been involved in research and development in the areas of: Computer Architecture, Reconfigurable Computing, VLSI Chip Design, Network-on-Chip, 3D chips, Sensor Networks, Computer Graphics, Memory and Embedded Systems. Bagherzadeh was named Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 2014[1] for contributions to the design and analysis of coarse-grained reconfigurable processor architectures. Bagherzadeh has published more than 400 articles in peer-reviewed journals and conferences. He was with AT&T Bell Labs from 1980 to 1984.
Education[edit]
- Ph.D., 1987 Computer Engineering University of Texas-Austin
- M.Sc., 1979 Electrical Engineering University of Texas-Austin
- B.Sc., 1977 Electrical Engineering University of Texas-Austin
Notable works[edit]
- MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications [2]
- Design and implementation of the MorphoSys reconfigurable computing processor [3]
- Power-aware scheduling under timing constraints for mission-critical embedded systems [4]
- Optimal Ring Embedding in Hypercubes with Faulty Links
- A scalable register file architecture for dynamically scheduled processors[5]
- A framework for reconfigurable computing: task scheduling and context management [6]
- Performance study of a multithreaded superscalar microprocessor [7]
Awards[edit]
- 2014, Khwarizmi International Award (27th Session)[8]
- 2002, Best paper award in IEEE Transactions on VLSI Design (TVLSI)
- 2002, Best paper award in the proceedings of Asia and South Pacific Design Automation Conference (ASPDAC)
References[edit]
- ^ "2014 Elevated Fellow". IEEE Fellows Directory.
- ^ Singh, H.; Ming-Hau Lee; Guangming Lu; Kurdahi, F.J.; Bagherzadeh, N.; Chaves Filho, E.M. (May 2000). "MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications". IEEE Transactions on Computers. 49 (5): 465–481. doi:10.1109/12.859540.
- ^ Lee, Ming-Hau; Singh, Hartej; Lu, Guangming; Bagherzadeh, Nader; Kurdahi, Fadi J.; Filho, Eliseu M. C.; Alves, Vladimir Castro (2000). "Design and Implementation of the MorphoSys Reconfigurable Computing Processor". Field-Programmable Custom Computing Technology: Architectures, Tools, and Applications. Springer, Boston, MA. pp. 21–38. CiteSeerX 10.1.1.37.3761. doi:10.1007/978-1-4615-4417-3_3. ISBN 978-1-4613-6988-2.
- ^ Liu, Jinfeng; Chou, Pai H.; Bagherzadeh, Nader; Kurdahi, Fadi (2001). "Power-aware scheduling under timing constraints for mission-critical embedded systems". Proceedings of the 38th conference on Design automation - DAC '01. ACM. pp. 840–845. doi:10.1145/378239.379076. ISBN 978-1581132977. S2CID 1100335.
- ^ Wallace, S.; Bagherzadeh, N. (20 October 1996). "A scalable register file architecture for dynamically scheduled processors". Proceedings of the 1996 Conference on Parallel Architectures and Compilation Technique. pp. 179–184. CiteSeerX 10.1.1.38.8935. doi:10.1109/pact.1996.552666. ISBN 978-0-8186-7632-1. S2CID 10188631.
- ^ Maestre, R.; Kurdahi, F.J.; Fernandez, M.; Hermida, R.; Bagherzadeh, N.; Singh, H. (December 2001). "A framework for reconfigurable computing: task scheduling and context management". IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 9 (6): 858–873. doi:10.1109/92.974899. S2CID 7073491.
- ^ Gulati, M.; Bagherzadeh, N. (3 February 1996). "Performance study of a multithreaded superscalar microprocessor". Proceedings. Second International Symposium on High-Performance Computer Architecture. pp. 291–301. CiteSeerX 10.1.1.51.984. doi:10.1109/hpca.1996.501194. ISBN 978-0-8186-7237-8. S2CID 1760177.
- ^ "Khwarizmi International Award 27th Session - 2014 | Khwarizmi International Award (KIA)". ip.irost.org.
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