Talk:Binary multiplier

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Misc[edit]

The 4 bit by 4 bit multiplier figure looks flawed - namely, the ordering of the bits of Multiplicand B is reversed when they enter 2nd and 3rd adders.

Fixed. Quart $parcialprouducts<sub><sub><sub>t</sub>$ (talk) 20:47, 17 March 2010 (UTC)[reply]

The fixed version is a 4 bit multiplier, it was reverted for the time being. Once it is reverted I suggest we do an article rewrite because it doesn't really match the style of other pages, and its kind of hard to read.Deadcellplus (talk) 20:26, 13 October 2008 (UTC)[reply]

Multiply Instruction Bit Sizes[edit]

Microprocessor Integer Multiply Instruction Bit Sizes
Microprocessor	8 x 8 = 16	16 x 16 = 32	32 x 16 = 32	32 x 32 = 32	32 x 32 = 64	64 x 64 = 64	64 x 64 = 128
ARM (older cores)		Yes*	Yes*	Yes	Yes
ARM Cortex-M0/M0+/M1				Yes
ARM Cortex-M3/M4/M7		Yes*	Yes*	Yes	Yes
ARM Cortex-A & Cortex-R		Yes*	Yes*	Yes	Yes
ARM Cortex-A53/A57 (ARMv8-A)				Yes	Yes	Yes	Yes*
Atmel AVR32				Yes	Yes
Microchip PIC32				Yes	Yes
Motorola 6809	Yes

Note: ARM Cortex-A53/A57 (ARMv8-A) requires an extra instruction to create the 128-bit result.

I'm considering adding this table to the first section. It still needs further expansion. Thoughts? • Sbmeirow • Talk • 01:21, 28 January 2015 (UTC)[reply]

Refs, x[edit]

This edit request has been answered. Set the |answered= or |ans= parameter to no to reactivate your request.

Please change all instances of the letter x used as a multiplication sign to ×.|Please markup the link in the first section as a ref. — Preceding unsigned comment added by 109.70.40.55 (talk)

Not done: According to the page's protection level you should be able to edit the page yourself. If you seem to be unable to, please reopen the request with further details. ‑‑ElHef (Meep?) 20:27, 9 April 2022 (UTC)[reply]

Redundant gate in 2×2 bit multiplier schematic[edit]

The AND in the second column generates (A0∧B1)∧(A1∧B0): the AND of all four inputs, the only way to get a product of 8 or higher, perfect for C3. Anding in any other AND of inputs, including the A1∧B1 shown, changes nothing. 188.109.124.100 (talk) 16:45, 29 July 2023 (UTC)[reply]

Not just that, the bottom-most AND gate (generating A1^B1) is also unneeded. The XOR generating C2 can be done as (A0∧B1)⊕(A1∧B0). D0SBoots (talk) 10:16, 18 November 2023 (UTC)[reply]