Talk:Intel X58

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Is ECC supported on the X50 chipset? mickrussom (talk) 21:11, 4 November 2008 (UTC)[reply]

The X58 does not have any memory interfaces. In the Quickpath architecture, memory is directly connected to the processor chip. therefore, ECC is irrelevant to the X58. the X58 does support one or two QPIs. QPI does have an error detection and recovery scheme and even a degraded mode to operate when a signal path fails, but this is not ECC. - Arch dude (talk) 21:22, 4 November 2008 (UTC)[reply]

VT-d

Does it support VT-d? Until recently only a few selected Q45 board supported VT-d for PCIe.

This could be a great breakthrough in using your GPU natively in virtual machines. 85.125.231.26 (talk) 19:24, 17 November 2008 (UTC)[reply]

Intel say YES (http://ark.intel.com/Platforms.aspx?platform=40420&mode=true)Stasdm (talk) 11:17, 21 January 2009 (UTC)[reply]

Lucid Hydra on Intel X58 revision...

http://www.theinquirer.net/inquirer/news/117/1050117/intel-puts-lucid-hydra-on-x58

omg this is gonna be awesome!!

please add it to the article —Preceding unsigned comment added by 189.165.88.177 (talk) 01:40, 21 December 2008 (UTC)[reply]

SLI

Do not think that SLI has anything to do with this article. SLI is a pure software technology and SLI patent is valid only in the USA.Stasdm (talk) 08:20, 21 January 2009 (UTC)[reply]

removed ICH10 para

I remoted this paragraph:

A note on the ICH10/ICH10R southbridge: while Intel's diagrams often show the six PCIe x1 lanes as 500 MB/s each, this is misleading: they have added both directions of the fully duplex port. 500 MB/s suggests PCIe 2.0 (500 MB/s per lane per direction) but ICH10/ICH10R only has PCIe 1.1 (250 MB/s per lane per direction). Confusingly, unlike with the northbridge in the same diagrams, Intel doesn't specify the PCIe version on the southbridge; but it has been confirmed as version 1.1 only. This is odd since the DMI link between the northbridge and southbridge is effectively a PCIe 2.0 x4 port. It has been speculated that Intel deemed PCIe 1.1 to already saturate the DMI link, what with the 12 USB ports and 6 SATA II ports and audio traffic too.

this information might be useful in th eICH10 article, but it is not about the X58.

However the diagram in this article contains that misleading number. Anyone fancy redrawing it in a less misleading way (and preferablly as a SVG so it can be easilly edited in future)? Plugwash (talk) 13:05, 4 March 2010 (UTC)[reply]

Block Diagram Improvements

The diagram labels links with maximum throughput. However, some of these are sustained in (only) one direction and other sustain this by (only) using both directions. It could be helpful to note which is which. I.e. QPI and DMI are for two way, PCIe and SATA are one way.
The memory bandwidth is 8.5 GB/s, not Gb/s.
The ICH10 PCIe ports are 1.1, not 2. So bandwidth is 250MB/s each, not 500MB/s.
It might be helpful to make the X58 and ICH10 PCIe notations the same. Right the X58 says there is a PCIe 2 block with up to 36 lanes while the ICH10 syas there are 6 PCIe x1, each up to 500 [sic] MB/s. We could change this to either X58 showing 36 PCIe 2, each up to 500MB/s or ICH10 with a PCIe 1 block with up to 6 lanes. —Preceding unsigned comment added by 71.118.48.35 (talk) 21:27, 3 July 2010 (UTC)[reply]

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