Talk:Prefetch buffer

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This article was nominated for deletion on 14 March 2015 (UTC). The result of the discussion was merge to Dynamic random-access memory.

Text and/or other creative content from this version of Prefetch buffer was copied or moved into Synchronous dynamic random-access memory with this edit on 28 November 2015. The former page's history now serves to provide attribution for that content in the latter page, and it must not be deleted as long as the latter page exists.

Prefetch buffer not improved

um, have to point out that the prefetch buffer is not 'improved' with subsequent generations of DDR...as your other articles on DDR/DDR2/DDR3 indicate, latency is greater which is not an 'improvement'.

Relate to cache

Can the article explain some relation to cache memory or cache operations? —Preceding unsigned comment added by 187.66.85.35 (talk) 00:23, 8 March 2011 (UTC)[reply]

Prefetch buffers are entirely independent of cache. If a read is satisfied from a level of cache closer to the processor, then it won't reach the prefetch buffer. --David-Sarah Hopwood ⚥ (talk) 04:30, 29 July 2012 (UTC)[reply]

The article says 64 bit (4 bytes) word is read from ram, but actually an entire cache line is read in case of a cache miss. So, more like 64 bytes, common for a cache line. In this case size of the prefetch buffer is important - memory is always accessed in bigger chunks. 83.8.27.220 (talk) 08:42, 31 May 2013 (UTC)[reply]