User:Asgalon/LH5801

LH5801 The LH5801 is an 8-bit microprocessor unit (MPU) in static CMOS technology produced by the Sharp Corporation from around 1980 to mid/late 1980ies (exact dates to be researched). It was used in the Sharp PC-1500 pocket computer series.

Overview

LH5801 microprocessor (above) with LH5810 I/O chip below on a Sharp PC-1500 motherboard

The processor features an 8-bit wide data bus and 16 bit wide address bus, which allows 64KB of main memory. A 1-bit memory enable signal allows addressing of a further 64KB of external memory in direct access for a total of 128KB capacity. The processor has 3 16-bit exclusive registers P, S and W, an 8-bit accumulator, 8 bit status register and 3 general purpose 16-bit registers named U, X and Y, which can be addressed as separate 8-bit registers (for example U_L and U_H). The processor has a timer function, three types of interrupt (Maskable, non-maskable and timer), DMA and multiprocessor capabilities, memory access control functionality, an 8-bit input port with clock signal for external latch, memory backup function and LCD back plate control..

The processor works with a clock rate of 2.6MHz which yields an internal machine cycle of 1.3MHz for a minimum instruction execution time of 1.3µs for single cycle instructions.

History

The actual release date has to be researched, probably around 1980. Detailed information about the processor were made available to the public in English in 1983, before that most users were restricted to using BASIC as programming language in the pocket computers using this CPU.

Architecture

The processor is an 8-bit CISC CPU with a basic design similar to the Z80, but with additional I/O capabilities such as direct LCD display control circuitry and connectors, targeted for its main usage in Sharp' series of pocket computers.

Block diagram

The block diagram was published in the PC-1500 Technical Reference Manual in 1983.

Internal Registers

PH 8	PL 8	P	Program counter
SH 8	SL 8	S	Stack pointer
UH 8	UL 8	Ureg	Data pointer or general purpose registers
XH 8	XL 8	Xreg
YH 8	YL 8	Yreg
	A 8	A	Accumulator
TM 9		TM	Timer
	1	PU	General purpose flipflop
	1	PV
	1	DISP	LCD on/off control

Status Flags

MSB							LSB
0	0	0	H	V	Z	IE	C

Flag	Name	Description
H	Half Carry	Set on overflow between lower and higher nibble, e.g. in BCD arithmetic.
V	Overflow	Set on overflow between bit 6 and 7 (change of sign)
Z	Zero	Set if operation result is zero
IE	Interrupt enable
C	Carry	Set on carry from most significant bit 7, else reset. on substraction when 'borrowed'.

Connectors

The processor as used in the Sharp PC-1500 is packaged in a 76 pin QFP variant (missing detailed measurements/documentation). The pins are numbered counterclockwise starting with the dot-marked corner.

No.	Name	Description
1	RESET	HIGH input for reset to initial state
2	-
3	BRQ	Bus request. MPU sets BAK to high when current command execution is completed
4	BF1	BF flipflop output
5	Vcc
6	BF0	BF flipflop input
7	OPF	Operation code fetch signal, high during fetch of instruction code byte
8	BAK	Bus acknowledge appears in response with a high BRQ indicating that address bus, data bus, R/W, ME0 and ME1 are in high impedance
9	Vcc	Voltage supply
10	-
11	VM	LCD drive source
12	VDID
13	VA
14	VB
15	NMI	Non maskable interrupt
16	MI	Maskable interrupt
17	¬HIN	LCD backplate signal. Counter input htat generates H0~H7. Normally connected to HA
18	HA	MPU divider output
19	DIS	Flipflop: Set to high with the SDP instruction and set to low with the RDP instruction
20	H7	LCD backplate signal
21	H6
22	H5
23	H4
24	H3
25	H2
26	H1
27	H0
28	OD	Output disable. When the OD signal is active the data bus is in the output mode.
29	ME0	Memory enable signals that the MPU uses for direct accessing to an external memory.
30	ME1
31	D0	Bidirectional data bus. D0: LSB, D7 MSB.
32	D1
33	D2
34	D3
35	D4
36	D5
37	D6
38	D7
39	AD0	16 bit address bus. AD0: LSB, AD15 MSB. Turns hign impedance by the BRQ signal.
40	AD1
41	AD2
42	AD3
43	AD4
44	AD5
45	AD6
46	AD7
47	GND
48	AD8
49	-
50	AD9
51	AD10
52	AD11
53	AD12
54	AD13
55	AD14
56	AD15
57	-
58	R/¬W	Read/Write signal, Read = 1 and write = 0
59	Pø	Strobe output during execution of ATP instruction for externallatch of A register contents.
60	PV	Flipflop: Set to high with the SPV instruction and set to low with the RPV instruction
61	PU	Flipflop: Set to high with the SPU instruction and set to low with the RPU instruction
62	øOS	Clock in same phase as basic internal clock, 1.3MHz frequenca when XL0 and XL1 are connected to a 2.6MHz quartz.
63	XL0	Crystal oscillator externel connection pins (XL0:in, XL1: out
64	XL1
65	WAIT	Wait input that informs the MPU that addressed memory or I/O device is not ready. The MPU is in the wait state while this isgnal is on.
66	IN7	Input port. Input is taken into internal accumulator as 8 bit data.
67	IN6
68	IN5
69	IN4
70	IN3
71	IN2
72	IN1
73	IN0
74	-
75	-
76	-

Instruction Set

Address modes

The names are inserted here for clarification and are not taken from original documentation.

Syntax	Name	Description	Example
i	Immediate	Use byte immediately following instruction	ADI A, 20H
A	Accumulator	Use Accumulator as operand	ADI A, 20H
i,j	Immediate, 16bit	16bit immediate, first byte i=MSB, second j=LSB	JMP A0H, 20H
RL	Register low direct	For register R, use content of lower byte.	ADC YL
RH	Register high direct	For register R, use content of higher byte.	ADC YH
(Rreg)	Register indirect	Use memory referenced by content of 16 bit register R	ADC (Xreg)
# (Rreg)	Register indirect ME 1	Same as register indirect, but with Memory Enabled pin 1	ADC # (Xreg)
(ab)	Indirect	Content from memory address ab (a MSB, b LSB)	ADC (C000H)
# (ab)	Indirect ME 1	Content from ME 1 address ab	ADC # (C000H)

Addition, Substraction and logical operations

Mnemonic	Operation	Description	Status bits affected	Address modes
ADC	Add with Carry	Operand will be added to acumulator with carry	C H Z V	Mode Opcode 7 6 5 4 3 2 1 0 RL 0 0 r r 0 0 1 0 RH 1 0 r r 0 0 1 0 (Rreg) 0 0 r r 0 0 1 1 # (Rreg) FD 0 0 r r 0 0 1 1 (ab) 1 0 1 0 0 0 1 1 # (ab) FD 1 0 1 0 0 0 1 1
ADI	Add immediately with carry	Immediate value will be added to first operand with carry	C H Z V	Mode Opcode 7 6 5 4 3 2 1 0 A,i 1 0 1 1 0 0 1 1 (R),i 0 1 r r 1 1 1 1 (ab),i 1 1 1 0 1 1 1 1 # (R),i FD 0 1 r r 1 1 1 1 # (ab),i FD 1 1 1 0 1 1 1 1
DCA	Decimal Add	Decimal addition betwen accumulator and operand.	C H Z V	Mode Opcode 7 6 5 4 3 2 1 0 (Rreg) 1 0 r r 1 1 0 0 # (Rreg) FD 1 0 r r 1 1 0 0

External links

• http://www.sharp.co.jp/
• http://www.pc1500.com/technical_reference_manual.html
• http://www.pc1500.com/assemblylanguage.html
• http://www.pc-1500.info/lh5801-microprocessor/