User:Nikitak.entc

          superscalar architecture

      The superscalar architecture is the main advancement used in Pentium processors.Due to suoerscalar architecture  the numeric co-processor oprates about 5 times faster than earlier used 80486 micropocessor. The improvement includes cache structure,a wider data bus,faster numeric coprocesso,a dual interger processor,branch prediction logic.
      Superscalar architecture consists of three execution unit.One executes floating point instruction.Other two U-pipe and V-pipe which execute integer insturction.

Thus two/three instructions can be executed simultaneously Example:FADD ST,ST(2) MOV EAX,10H MOV EBX,10H -----All these instruction can be executed simultaneously because none of these instruction depend on one another. First instruction is executed by coprocessor and other two instruction are executed by u-pipe and v-pipe.

      Software should be written to take advantage of this feature by looking at the instruction in a program,and modifyingthem when cases are,discovered,where dependent instruction are seperate by non-dependent instructions.These changes can result upto 40% execution speed improvment in some software.
         The integer pipelines U and V,where each one is a 5-stage pipeline.These are similar to one of 80846 CPU.

Following are the function of the pipelines:

1.In the prefetch stage of the pipeline,the CPU fetches the instruction from the instruction cache,which stores the instruction to be executed .In this stage,the pentium also assigns thecode appropirately.This is required since the instruction are of variable length and initial opcode bytes of each instruction should be appropriately aligned.After the prefetch stage,there are two decode stages D1 and D2. 2.In the D1 stage the pentium decodes the instruction and generates a control word. 3.Thus a second decode stage D2 is required where the controlword from D1 stage again decoded for final execution .Also the pentium generates address for data memory refrences in this stage. 4.In the execution stage,known as E-stage,the Pentium either accesses the data cache for data operands or executes the arithmetic/logic computations or floating-point operations in the execution unit. 5.In the final five stage pipeline,which is the WB(write back) stage,the Pentium updates the register contents of the flag register depending upon the execution result.