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|Binary floating point precision|
|Decimal floating point precision|
In computer architecture, 36-bit integers, memory addresses, or other data units are those that are 36 bits (six six-bit characters) wide. Also, 36-bit CPU and ALU architectures are those that are based on registers, address buses, or data buses of that size.
Prior to the introduction of computers, the state of the art in precision scientific and engineering calculation was the ten-digit, electrically powered, mechanical calculator, such as those manufactured by Friden, Marchant and Monroe. These calculators had a column of keys for each digit, and operators were trained to use all their fingers when entering numbers, so while some specialized calculators had more columns, ten was a practical limit. Computers, as the new competitor, had to match that accuracy. Decimal computers sold in that era, such as the IBM 650 and the IBM 7070, had a word length of ten digits, as did ENIAC, one of the earliest computers.
Early binary computers aimed at the same market therefore often used a 36-bit word length. This was long enough to represent positive and negative integers to an accuracy of ten decimal digits (35 bits would have been the minimum). It also allowed the storage of six alphanumeric characters encoded in a six-bit character code. Computers with 36-bit words included the MIT Lincoln Laboratory TX-2, the IBM 701/704/709/7090/7094, the UNIVAC 1103/1103A/1105, the UNIVAC 1100/2200, the General Electric GE-600/Honeywell 6000, the Digital Equipment Corporation PDP-6/PDP-10 (as used in the DECsystem-10/DECSYSTEM-20), and the Symbolics 3600 series.
These computers had addresses 15 to 18 bits in length. The addresses referred to 36-bit words, so the computers were limited to addressing between 768 and 32144 words ( 262608 to 196572864 six-bit characters). The older 36-bit computers were limited to a similar amount of physical memory as well. Architectures that survived evolved over time to support larger virtual address spaces using 1memory segmentation or other mechanisms.
The common character packings included:
- six 5.32-bit DEC Radix-50 characters, plus four spare bits
- six 6-bit Fieldata or IBM BCD characters (ubiquitous in early usage)
- six 6-bit ASCII characters, supporting the upper-case unaccented letters, digits, space, and most ASCII punctuation characters. It was used on the PDP-6 and PDP-10 under the name sixbit.
- five 7-bit characters and 1 unused bit (the usual PDP-6/10 convention, called five-seven ASCII)
- four 8-bit characters (7-bit ASCII plus 1 spare bit, or 8-bit EBCDIC), plus four spare bits
- four 9-bit characters (the Multics convention).
Characters were extracted from words either using machine code shift and mask operations or with special-purpose hardware supporting 6-bit, 9-bit, or variable-length characters. The Univac 1100/2200 used the partial word designator of the instruction, the "J" field, to access characters. The GE-600 used special indirect words to access 6- and 9-bit characters. the PDP-6/10 had special instructions to access arbitrary-length byte fields.
The standard C programming language requires that the size of the
char data type be at least 8 bits, and that all data types other than bitfields have a size that is a multiple of the character size, so standard C implementations on 36-bit machines would typically use 9-bit
chars, although 12-bit, 18-bit, or 36-bit would also satisfy the requirements of the standard.
By the time IBM introduced System/360, scientific calculations had shifted to floating point and mechanical calculators were no longer a competitor. The 360s also included instructions for variable length decimal arithmetic for commercial applications, so the practice of using word lengths that were a power of two quickly became commonplace, though some 36-bit computer systems are still sold as of 2014[update], e.g., the Unisys ClearPath Dorado series, which is the continuation of the UNIVAC 1100/2200 series of mainframe computers.
Other uses in electronics
The LatticeECP3 FPGAs from Lattice Semiconductor include multiplier slices that can be configured to support the multiplication of two 36-bit numbers. The DSP block in Altera Stratix FPGAs can do 36-bit additions and multiplications.
- Marshall Cline. "Would you please go over the rules about bytes, chars, and characters one more time?"
- RFC 114: "A file transfer protocol"
- ISO/IEC 9899:1999 specification. p. 20, § 126.96.36.199.1.
- ISO/IEC 9899:1999 specification. p. 37, § 188.8.131.52 (4).
- Marshall Cline. "C++ FAQ: the rules about bytes, chars, and characters".
- "LatticeECP3 sysDSP Usage Guide" (PDF). Lattice Semiconductor. Retrieved December 27, 2013.
- "Digital Signal Processing (DSP) Blocks in Stratix Devices". Altera+accessdate=December 27, 2013.