Talk:Emotion Engine

Cruise missiles

Hey, I remember there was much panic in the press about Saddam and Kim of Korea using these EE chips stripped from PS2 consoles to make cheap precision cruise missile warheads and annule western military technology superiority. That could be discussed. 195.70.32.136 19:04, 13 March 2006 (UTC)

Be my guest (but cite references). Diceman 16:03, 14 March 2006 (UTC)

You could guide a cruise missile with a 6502. It isn't rocket science. Well, okay, technically, it is, but it doesn't require much CPU horsepower. ;) The concern about 'rogue states' getting supercomputers is that they would be able to do nuclear warhead simulation/design with them. However, I suspect you have to do some real-world nuke testing to know that your simulations are accurate -- in other words, you already have to be able to build a nuke, but a supercomputer can help you build a better/more compact/more efficient one. Today, surplus Pentium III CPUs might be a better bet for rogue state supercomputer development. Kaleja 05:21, 16 September 2006 (UTC)

heard about this as well from my ECE prof. he said it's illegal to import PS2 to certain countries. -- Bubbachuck (talk) 16:53, 30 December 2007 (UTC)

Apple used the same marketing. It's true in some regards but obviously non-sense, http://www.tekrevue.com/apples-1999-power-mac-g4-really-classified-weapon/ --71.237.236.28 (talk) 18:58, 9 February 2015 (UTC)

What about the PS3? Is it illegal to import that too? — Preceding unsigned comment added by 24.180.93.29 (talk) 17:38, 5 August 2012 (UTC)

Really a 128 bit processor?

Is this cpu >really< a 128 bit one? Some people think that ee is a 32 bit processor, and that the 128 bit thing is a marketing argument.

For instance, all pentium 3/athlon xp processors have 128 bit instructions (simd sse) but they remain being 32 bit processors. Isn't the same with the ee? Licurgo 04:15, 5 June 2006 (UTC)

The MIPS R5900 core is 64 bits for sure, the vector units are probably 128 bits, but I don't think this qualify the EE as a 128 bit processor. --Pezezin 23:11, 28 June 2006 (UTC)

Well this should be reflected on the article, because it says 128 bits everywere and it isn't true. Thanks for answering. --Licurgo 03:24, 8 July 2006 (UTC)

The core register set has been extended from 64 to 128 bit width. A single instruction can do a 128-bit read or write. Pointer width is 32-bit; address space might be 64-bit but it's a moot point because there's quite a bit less than 4GB of addressable memory. The integer math unit is 64-bit (as stated in the article), and I can't say for sure what the internal bus widths are. It's very hard to boil a modern complex CPU down to a single number describing its bit width, but it's not pure marketingese to say that EE is 128-bit. Kaleja 05:12, 16 September 2006 (UTC)

IMO the 128 bit processor thing should be dropped and replaced with something about the width of the SIMD units. Its rather misleading the way its currently phrased.

FLOPS confusion

From the article it descibes a maximum of 14 FLOPS per clock. 14 FLOPS per clock * 294/299Mhz = 4.116/4.186 GigaFLOPS not 6.2. whats up with that? Also from my understanding a 733 Mhz PIII with one vec4 unit and and one scalar FPU has a max of 3.665 GigaFLOPS, not hardly one half the FLOPS power, and combinded in to a single thread ,and WAY less total instructions per clock, to boot. However that doesnt count in the poor implementation of MMX in the PIII, but this about theoretical numbers. and the 400mhz Celeron would have to be PII based to be anywhere close to that slow.

If you read the FLOPS article you'll notice that theoretical stats are rarely or not usually attained. I don't even see why the theoretical performance is even listed for the emotion engine; it's just a possible number that could be associated with the chip. --Trakon (talk) 05:28, 10 June 2008 (UTC)

The theoretical performance is specified so we can compare it to benchmarked performance to see the difference. Doing so is very useful for comparing architectural choices and a hundred other things. It is common practice to do so - you will find that technical papers do this as does the TOP500. Rilak (talk) 06:33, 11 June 2008 (UTC)

Article too technical

I'm currently attempting to make the article more assessable, as request by an editor who placed a "too technical" tag at the top of this article. I've attempted to fix what I see as being being technical, but it would be most helpful if someone could read the article and list what statements are problematic below, as two pairs of eyes are better than one. Rilak (talk) 07:17, 18 July 2008 (UTC)

Problems

• <List here!>

2.4 GiB/s <> 2.4 GB/s

Someone changed GiB/s units to GB/s without changing the numerical value. Changing the unit without changing the numerical value is not justified unless the old values were wrong. Does anyone know the correct values? Thunderbird2 (talk) 13:37, 18 July 2008 (UTC)

2.4 GB/s. The GiB values were a blind application of the IEC prefixes [1]. Headbomb {ταλκ – WP Physics: PotW} 13:49, 18 July 2008 (UTC)

That link shows the original as 2.4 GT/s. I agree that 2.4 GiB/s would then be wrong, but why is 2.4 GB/s any better? How many bytes or bits are involved in each transfer? Thunderbird2 (talk) 14:06, 18 July 2008 (UTC)

This page explains things fairly well. Headbomb {ταλκ – WP Physics: PotW} 14:10, 18 July 2008 (UTC)

If that page is correct, it means that 2.4 GT/s = 0.24 GB/s, so all the values would be out by a factor of 10. Thunderbird2 (talk) 14:19, 18 July 2008 (UTC)

More like 2.4 GT/s = 2.4 Gbit/s = 0.3 decimal GB/s. Effective transfer rate would be (if the 8/10 thing applies) 1.92 Gbit/s or 0.24 decimal GB/s. It's probably best to put things in GT/s. Headbomb {ταλκ – WP Physics: PotW} 14:27, 18 July 2008 (UTC)

agreed. Thunderbird2 (talk) 14:39, 18 July 2008 (UTC)

The Microprocessor Report article (whose details can be found under the "References" section of this article), was used as the primary source for this article. It states very clearly, in Figure 3. on page two, that the bus runs at "2.4 GB/s". Very clearly. This is an exact quote from the article. This figure is further supported by the fact that it is a 128-bit bus clocked at 150 MHz, therefore (128/8) * 150 = 2400 [MB], if you do the math. 2400/1000 = 2.4. Unless my math is shockingly bad, it seems that 2.4 GB/s is correct. The source supports it, the theory supports it. Do we need a four or more page debate and a RFC now? Rilak (talk) 05:43, 19 July 2008 (UTC)

If that's what the source says, and there are no conflicting sources, that's what the article should say. Does your comment apply to all the other values given in GT/s and MT/s? (there are several) Thunderbird2 (talk) 08:23, 19 July 2008 (UTC)

Yes, my comments do apply to the other values (I didn't notice them when I posted my previous message. If anyone wants sources, they can be found in the Microprocessor Report article in the "References" section of the article. Googling for the title should produce a few online copies of the article, that is how I found it in the first place. I simply do not understand how my edits resulted in discussion. Unless I am mistaken, binary prefixes are usually incorrect for measuring the bandwidth of a bus, and GT/s is usually applied to buses that transfer more than once in a single clock cycle. Rilak (talk) 08:59, 19 July 2008 (UTC)

Sorry - I didn't realise you were just correcting an error (your edit summary was a little cryptic). Thunderbird2 (talk) 09:09, 19 July 2008 (UTC)

Tried to fix it - is it OK now? Thunderbird2 (talk) 09:18, 19 July 2008 (UTC)

Yes, its fine now. You're right about my edit summary though, it wasn't very descriptive. Sorry about that. Rilak (talk) 09:42, 19 July 2008 (UTC)

Etymology of the name

Where does the name "Emotion Engine" come from? That is the only reason I clicked on this article from the PS2 article. I thought it was an odd name and wondered what the significance was. Brendanmccabe (talk) 23:09, 16 August 2010 (UTC)

I recall some old marketing non-sense talking about how it's the first CPU advanced enough to "simulate real emotions," ie, the avatars will have simulated emotions. No source on that and google isn't turning up anything. --71.237.236.28 (talk) 18:54, 9 February 2015 (UTC)

PS3 hardware choices

The first PS3 actually had the EE+GS chip. EE+GS was a die-shrink that had both the Emotion Engine and the Graphics Synthesizer cores on the same die. Later PS3 revisions had the GSX chip, which was one of the earlier die-shrink variants of just the GS prior to the EE+GS. Ohmantics (talk) 19:08, 22 October 2015 (UTC)

The same thing happened with the PS2 later on. PlayStation 2 hardware has pictures of EE+GS integrated ASICS, some which also contained the EE+GS+system memory.

I think the GSX was the GS+system memory.

You could have a paragraph to explain that with later PS2s, and PS3s with the EE, the EE+GS where integrated. Not that it really mattered from a functional point of view. Best to get sources though. --Jules (Mrjulesd) 21:06, 22 October 2015 (UTC)

External links modified

Hello fellow Wikipedians,

I have just modified one external link on Emotion Engine. Please take a moment to review my edit. If you have any questions, or need the bot to ignore the links, or the page altogether, please visit this simple FaQ for additional information. I made the following changes:

• Added archive https://web.archive.org/web/20041120084657/http://arrakis.ncsa.uiuc.edu/ps2/ to http://arrakis.ncsa.uiuc.edu/ps2/

When you have finished reviewing my changes, you may follow the instructions on the template below to fix any issues with the URLs.

This message was posted before February 2018. After February 2018, "External links modified" talk page sections are no longer generated or monitored by InternetArchiveBot. No special action is required regarding these talk page notices, other than regular verification using the archive tool instructions below. Editors have permission to delete these "External links modified" talk page sections if they want to de-clutter talk pages, but see the RfC before doing mass systematic removals. This message is updated dynamically through the template {{source check}} (last update: 18 January 2022).

• If you have discovered URLs which were erroneously considered dead by the bot, you can report them with this tool.
• If you found an error with any archives or the URLs themselves, you can fix them with this tool.

Cheers.—InternetArchiveBot (Report bug) 15:46, 20 September 2017 (UTC)

Main technical article on the CPU

DISCLAIMER: I am an author of the article given below (and a co-designer of the chip). Therefore it would be a conflict of interest for me to place this reference into the article myself. I'll leave it to the rest of you to decide.

The main technical article on the R5900 CPU was: F.M. Raam, R. Agarwal, K. Malik, H.A. Landman, H. Tago, T. Teruyama, T. Sakamoto, T. Yoshida, S. Yoshioka, Y. Fujimoto, T. Kobayashi, T. Hiroi, M. Oka, A. Ohba, M. Suzuoki, T. Yutaka, Y. Yamamoto, "A High Bandwidth Superscalar Microprocessor for Multimedia Applications", 1999 International Solid-State Circuits Conference, Digest of Technical Papers, pp.258-259. http://ieeexplore.ieee.org/document/759231/ DOI: 10.1109/ISSCC.1999.759231

Note that the CPU was only about 45% of the total chip area, so this paper only describes about half of the Emotion Engine. But I still think it should be a reference in the article.

Howard Landman (talk) 08:28, 7 December 2017 (UTC)