Emotion Engine

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Sony Emotion Engine CPU

The Emotion Engine is a CPU developed and manufactured by Sony and Toshiba for use in the Sony PlayStation 2 video game console. Mass production of the Emotion Engine began in 1999.

Contents

[edit] Description

The Emotion Engine consists of eight separate "units", each performing a specific task, integrated onto the same die. These units are: a MIPS-based core, two Vector Processing Units (VPU), a graphics interface (GIF), a 10 channel DMA unit, a memory controller, an Image Processing Unit (IPU) and an input output interface.

[edit] MIPS core

At the heart of the Emotion Engine is a two-way superscalar in order MIPS-based core primarily based on the MIPS-III Instruction Set Architecture (MIPS-III ISA) but includes some instructions defined by the MIPS-IV ISA. The MIPS-based core consists of two 64-bit arithmetic logic units (ALU) and a single precision (32-bit) floating point unit (FPU). The ALU and the FPU pipelines are both six stages long.

To feed the execution units with instructions and data, there is a 16 KB two-way set associative instruction cache, an 8 KB[1] two-way set associative non blocking data cache and a 16 KB scratchpad RAM. Both the instruction and data caches are virtually indexed and physically tagged while the scratchpad RAM exists in a separate memory space. A combined 48 double entry instruction and data translation lookaside buffer is provided for translating virtual addresses. Branch prediction is achieved by a 64-entry branch target address cache and a branch history table that is integrated into the instruction cache. The branch mispredict penalty is three cycles due to the short six stage pipeline.

[edit] Vector processing units

The majority of the Emotion Engine's floating point performance is provided by two vector processing units (VPU), designated VPU0 and VPU1. Each VPU features 32 128-bit registers, 16 16-bit fixed-point registers, four FMAC (Floating point Multiply-ACcumulate) units, an FDIV (Floating point DIVide) unit and a local data memory. The data memory for VPU0 is 4 KB in size, while VPU1 features a 16 KB data memory.

To achieve high bandwidth, the VPU's data memory is connected directly to the GIF, and both of the data memories can be read directly by the DMA unit. A single vector instruction consists of four 32-bit IEEE compliant single-precision floating-point values which are distributed to the four single-precision (32-bit) FMAC units for processing. Contrary to popular belief, the Emotion Engine is not a 128-bit processor as it does not process a single 128-bit value, but a group of four 32-bit values that are stored in one 128-bit register.[2][3] This scheme is similar to the SSEx extensions by Intel.

The FMAC units take four cycles to execute one instruction, but as the units have a six-stage pipeline, they have a throughput of one instruction per cycle. The FDIV unit has a nine-stage pipeline and can execute one instruction every seven cycles.

[edit] Internal data bus

Communications between the MIPS core, the two VPUs, GIF, memory controller and other units is handled by a 128-bit wide internal data bus running at half the clock frequency of the Emotion Engine. At 300 MHz, the internal data bus provides a maximum theoretical bandwidth of 2.4 GB/s[4]. DMA transfers over this bus occurs in packets of eight 128-bit words, achieving a peak bandwidth of 2 GB/s[3].

[edit] External interface

Communication between the Emotion Engine and RAM occurs through two channels of DRDRAM (Direct Rambus Dynamic Random Access Memory) and the memory controller, which interfaces to the internal data bus. The two channels of DRDRAM have a maximum theoretical bandwidth of 3.2 GB/s, about 33% more bandwidth than the internal data bus. Because of this, the memory controller buffers data sent from the DRDRAM channels so the extra bandwidth can be utilised by the CPU.

The Emotion Engine interfaces directly to the Graphics Synthesizer via the GIF with a dedicated 64-bit, 150 MHz bus that has a maximum theoretical bandwidth of 1.2 GB/s[3]

To provide communications between the Emotion Engine and the Input Output Processor (IOP), the input output interface interfaces a 32-bit wide, 37.5 MHz input output bus with a maximum theoretical bandwidth of 150 MB/s to the internal data bus. It should be noted that this interface provides vastly more bandwidth than what is required by the PlayStation's input output devices.

[edit] Uses

The primary use of the Emotion Engine was to serve as the PlayStation 2's CPU. The first versions of the PlayStation 3 also featured an Emotion Engine on the motherboard to achieve backwards compatibility with PlayStation and PlayStation 2 games. However, subsequent releases of the PlayStation 3 dropped the Emotion Engine to lower costs.

[edit] Specifications

  • Clock frequency: 294 MHz, 299 MHz (later versions)
  • Instruction set: MIPS III, MIPS IV subset, 107 vector instructions
  • MIPS based core: 2 issue, 2 64-bit fixed point units, 1 floating point unit, 6 stage pipeline
  • Instruction cache: 16 KB, 2-way set associative
  • Data cache: 8 KB, 2-way set associative
  • Scratchpad RAM: 16 KB
  • Translation look aside buffer: 48-entry combined instruction/data
  • Vector processing unit: 4 FMAC units, 1 FDIV unit
  • Vector processing unit registers: 128-bit wide, 32 entries
  • Image processing unit: MPEG2 macroblock layer decoder
  • Direct memory access: 10 channels
  • Internal data bus: 128 bit, 150 MHz, 2 GB/s maximum effective bandwidth
  • Memory bus: Two 16-bit, 400 MHz DRDRAM channels, 3.2 GB/s (maximum theoretical bandwidth)
  • Manufacturing process: 0.25 µm (0.18 µm effective LG, 4 layer metal, CMOS)
  • VDD Voltage: 1.8 V
  • Power consumption: 15 W at 1.8 V
  • Transistor count: 10.5 million
  • Die area: 240 mm2
  • Packaging: 540-contact PBGA

[edit] Theoretical performance

[edit] References

  1. ^ Transistorized memory, such as RAM and cache sizes (other than solid state disk devices such as USB drives, CompactFlash cards, and so on) as well as CD-based storage size are specified using binary meanings for K (10241), M (10242), G (10243), ...
  2. ^ John L. Hennessy and David A. Patterson. "Computer Architecture: A Quantitative Approach, Third Edition". ISBN 1-55860-724-2
  3. ^ a b c Keith Diefendorff. "Sony's Emotionally Charged Chip". The Microprocessor Report, Volume 13, Number 5, April 19, 1999. Microdesign Resources.
  4. ^ Disk-based memory (hard drives), solid state disk devices such as USB drives and CompactFlash cards, DVD-based storage, bus speeds, and network speeds, are specified using decimal meanings for K (10001), M (10002), G (10003), ...

[edit] See also

[edit] External links

Retrieved from "http://en.wikipedia.org/wiki/Emotion_Engine"
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